View 7512_4247303.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

7512 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0122-0101 Rev.1.01 Feb 18, 2005
DESCRIPTION
The 7512 Group is the 8-bit microcomputer based on the 740 family core technology. The 7512 Group is designed for battery-pack and includes serial interface functions, 8-bit timer, A/D converter, current integrator and I2C-BUS interface.
FEATURES
qBasic machine-language instructions ...................................... 71 qMinimum instruction execution time .................................. 1.0 s (at 4 MHz oscillation frequency) qMemory size Flash memory .................................................. 36 K to 52 Kbytes RAM ............................................................... 1.0 K to 1.5 Kbytes qProgrammable input/output ports ............................................ 36 qInterrupts ................................................. 19 sources, 16 vectors qTimers ............................................................................. 8-bit 4 qSerial interface Serial I/O1 .......... 8-bit 1 (UART or Clock-synchronized) Serial I/O2 .......................... 8-bit 1(Clock-synchronized) qMulti-master I2C-BUS interface (option) ...................... 1 channel qPWM ............................................................................... 8-bit 1 qA/D converter ............................................. 10-bit 10 channels
qCurrent integrator ......................................................... 1 channel qOver current detector ................................................... 1 channel qEasy thermal sensor .................................................... 1 channel qWatchdog timer ............................................................ 16-bit 1 qClock generating circuit ..................................... Built-in 4 circuits (high-speed RC oscillator and 32kHz RC oscillator, or connect to external ceramic resonator or quartz-crystal oscillator) qPower source voltage ............................................ 2.45 to 2.55 V qPower dissipation In high-speed mode ...................................................... 3.75 mW (at 4 MHz oscillation frequency, at 2.5 V power source voltage) In low-speed mode ........................................................ 1.05 mW (at 32 kHz oscillation frequency, at 2.5 V power source voltage) qOperating temperature range .................................... -20 to 85C
APPLICATION
Battery-Pack, etc.
P07/PWM1/AN11
PIN CONFIGURATION (TOP VIEW)
P01/SOUT2 P03/SRDY2 P02/SCLK2 P34/AN4 P35/AN5 P04/AN8 P00/SIN2 P05/AN9
P06/CFETCNT/AN10
P10/(LED0)
26
36
34
32
31
33
29
35
P33/AN3 P32/AN2 P31/AN1 P30/AN0 ADVSS ADVRED VCC AVCC AVSS ISENS0 ISENS1 DFETCNT/P45
37 38 39 40 41 42 43 44 45 46 47 48
30
28
27
25
P11/(LED1)
24 23 22 21 20
P12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P16/(LED6) P17/(LED7) VSS XOUT XIN RESET P20/XCOUT P21/XCIN
M37512FCHP
19 18 17 16 15 14 13
10
11
P44/INT3/PWM0
P27/CNTR0/SRDY1
P43/INT2/SCMP2
P24/SDA2/RXD
P40/CNTR1
P25/SCL2/TXD
P22/SDA1
P26/SCLK
P23/SCL1
P42/INT1
Package type : 48P6Q-A
Fig. 1 M37512FCHP pin configuration
Feb 18, 2005 page 1 of 85 REJ03B0122-0101
P41/INT0
CNVSS
12
1
7
3
2
4
5
6
8
9
7512 Group
FUNCTIONAL BLOCK DIAGRAM
Main-clock input X IN VSS VC
C 43 15 12 18
Main-clock output X OUT Reset input RESET CNVSS
Feb 18, 2005 page 2 of 85 REJ03B0122-0101
CPU
FUNCTIONAL BLOCK
Fig. 2 Functional block diagram
16
17
Clock generating circuit X
Prescaler 12 (8)
RAM ROM
Timer 2 (8) Timer Y ( 8 ) Timer Y ( 8 ) Y
Prescaler X (8)
A
Timer 2 (8)
XCIN sub-clock input
XCOUT sub-clock output
S
CNTR0 Prescaler Y (8)
PC H PCL PS
CNTR1
Easy thermal sensor
Watchdog timer
Reset
0
Over current detector SI/O1(8)
Current integrator I2 C (8)
10bit A/D converter
PWM (8)
SI/O2(8)
XCIN XCOUT INT0 - INT3
P4(6) P3(6)
P2(8)
P1(8)
P0(8)
ISENS1
35 36 37 38 39 40
AVcc
6 7 8 9 10 11 13 14 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
47 46 45 44
41 42
48 1 2 3 4 5
ISENS0 AVss
ADVSS ADVREF
I/O port P 4
I/O port P 3
I/O port P 2
I/O port P 1
I/O port P 0
7512 Group
PIN DESCRIPTION
Table 1 Pin description Pin VCC, VSS AVCC AVSS ADVSS ADVREF CNVSS RESET XIN XOUT Name Power source Analog power source Analog reference voltage CNVSS input Reset input Clock input Clock output Functions *Apply voltage of 2.5V to Vcc, and 0 V to Vss. *Apply voltage of 2.5V to AVcc, and 0 V to AVss, ADVss.
Function except a port function
*Reference voltage input pin for A/D converters. *This pin controls the operation mode of the chip. *Normally connected to VSS. *Reset input pin for active "L". *Input and output pins for the clock generating circuit. *Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. *When a high-speed RC oscillator is used, leave the XIN pin and XOUT pin open. *When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. * Serial I/O2 function pin *8-bit CMOS I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level. *P00 to P07 are CMOS 3-state output structure, and P10 to P17 are N-channel open-drain structure. *P10 to P17 (8 bits) are enabled to output large current for LED drive. * A/D converter input pin * A/D converter input pin / Over current detector function pin * A/D converter input pin / PWM output pin
P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04/AN8 P05/AN9 P06/CFETCNT/ AN10 P07/AN11/ PWM1 P10-P17 P20/XCOUT P21/XCIN P22/SDA1 P23/SCL1 P24/SDA2/RxD P25/SCL2/TxD P26/SCLK P27/CNTR0/ SRDY1 P30/AN0- P35/AN5
I/O port P0
I/O port P1 I/O port P2 *8-bit CMOS I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level, but P22 to P25 can be switched between CMOS compatible input level or SMBUS input level in the I2C-BUS interface function. *P20, P21, P26, P27: CMOS3-state output structure. *P22 to P25: N-channel open-drain structure. * Sub-clock generating circuit I/O pins (connect a resonat or registor and capacitor) * I2C-BUS interface function pins * I2C-BUS interface function pins/ Serial I/O1 function pins * Serial I/O1 function pin * Serial I/O1 function pin/ Timer X function pin * A/D converter input pin
I/O port P3
*6-bit CMOS I/O port with the same function as port P0. *CMOS compatible input level. *CMOS 3-state output structure.
P40/CNTR1 P41/INT0 P42/INT1 P43/INT2/SCMP2 P44/INT3/PWM0 P45/DFETCNT ISENS0 ISENS1
I/O port P4
*6-bit CMOS I/O port with the same function as port P0. *CMOS compatible input level. *P40 to P42, P45 are CMOS 3-state output structure, and P43 and P44 are N-channel open-drain structure.
* Timer Y function pin * Interrupt input pins * Interrupt input pin/SCMP2 output pin * Interrupt input pin/PWM output pin * Over current detector function pin
Analog input pin
*Current integrator and over current detector input pins. *Connect the sense resistor. Normally connect the ISENS0 to GND.
Feb 18, 2005 page 3 of 85 REJ03B0122-0101
7512 Group
GROUP EXPANSION
Renesas plans to expand the 7512 group as follows.
Memory Size
ROM size ........................................................... 36 K to 52 K bytes RAM size .......................................................... 1024 to 1536 bytes
Memory Type
Support for flash memory version.
Packages
48P6Q-A ............................................... 48-pin plastic molded QFP
Memory Expansion Plan
ROM size (bytes)
60K
Mass production
M37512FC
48K
Under development
M37512FCH
Mass production
M37512F8
32K
Under development
M37512F8H
768
1024
1280
1536
3072
RAM size (bytes)
Fig. 3 Memory expansion plan Currently planning products are listed below. Table 2 Support products Product name ROM size (bytes) RAM size (bytes) Package Remarks
M37512F8HP M37512F8-XXXHP 32K + 4K 1024 M37512F8HHP (Note 1) M37512F8H-XXXHP (Note 1) 48P6Q-A M37512FCHP M37512FC-XXXHP 48K + 4K 1536 M37512FCHHP (Note 1) M37512FCH-XXXHP (Note 1) Note 1. The products of which erase/write cycles onto the blocks A and B are maximum 10k are under development.
Feb 18, 2005 page 4 of 85 REJ03B0122-0101
7512 Group
FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU)
The 7512 Group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is "0" , the high-order 8 bits becomes "0016". If the stack page selection bit is "1", the high-order 8 bits becomes "0116". The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 5. Store registers other than those described in Figure 4 with program when the user needs them during interrupts or subroutine calls (see Table 3).
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data transfer, etc. are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address.
b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL
b0 Accumulator b0 Index register X b0 Index register Y b0 Stack pointer b0 Program counter b0 Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag
NVTBD I ZC
Fig.4 740 Family CPU register structure
Feb 18, 2005 page 5 of 85 REJ03B0122-0101
7512 Group
On-going Routine
Interrupt request (Note) Execute JSR M (S) Push return address on stack (S) M (S) (S) (PCH) (S) - 1 (PCL) (S)- 1
M (S) (S) M (S) (S) M (S) (S)
(PCH) (S) - 1 (PCL) (S) - 1 (PS) (S) - 1 Push contents of processor status register on stack Push return address on stack
Subroutine Execute RTS POP return address from stack (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S)
Interrupt Service Routine
Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) (S) + 1 M (S)
I Flag is set from "0" to "1" Fetch the jump vector
POP contents of processor status register from stack
POP return address from stack
Note: Condition for acceptance of an interrupt
Interrupt enable flag is "1" Interrupt disable flag is "0"
Fig. 5 Register push and pop at interrupt generation and subroutine call Table 3 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP
Feb 18, 2005 page 6 of 85 REJ03B0122-0101
7512 Group
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. *Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. *Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". *Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". *Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can execute decimal arithmetic.
*Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". *Bit 5: Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations. *Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. *Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag.
Table 4 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag - - I flag SEI CLI D flag SED CLD B flag - - T flag SET CLT V flag - CLV N flag - -
Feb 18, 2005 page 7 of 85 REJ03B0122-0101
7512 Group
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0: Not available 1 1: Stack page selection bit 0 : 0 page 1 : 1 page Clock source switch bit 0 : Built-in high speed oscillating function 1 : XCIN-XCOUT oscillation function Port XC switch bit 0 : I/O port function (stop oscillation) 1 : XCIN-XCOUT oscillation function Main clock (XIN-XOUT) stop bit 0 : Oscillation 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : = f(XIN)/2 (high-speed mode) 0 1 : = f(XIN)/8 (middle-speed mode) 1 0 : = f(XIN)/2 (low-speed mode) 1 1 : Not available
Note : All bits in this register are protected by protect mode.
Fig. 6 Structure of CPU mode register
Feb 18, 2005 page 8 of 85 REJ03B0122-0101
7512 Group
MEMORY Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
Access to this area with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
Special Page
Access to this area with only 2 bytes is possible in the special page addressing mode.
Flash Memory
The last 2 bytes of flash memory are reserved for device testing and the rest is user area for storing programs.
RAM size and area Product name M37512F8HP M37512F8-XXXHP M37512F8HHP M37512F8H-XXXHP M37512FCHP M37512FC-XXXHP M37512FCHHP M37512FCH-XXXHP RAM size (bytes) 1024 Address XXXX16 043F16
1536
063F16
ROM size and area (Except Data block) ROM size Product name (bytes) M37512F8HP M37512F8-XXXHP 32768 M37512F8HHP M37512F8H-XXXHP M37512FCHP M37512FC-XXXHP 49152 M37512FCHHP M37512FCH-XXXHP
Address YYYY16 800016
400016
User ROM area 000016 004016 010016 RAM SFR area Zero page
XXXX16 0FE016 0FFF16 100016 ROM 1FFF16
Not used SFR area
Not used YYYY16 F00016
Boot ROM area
FF0016 ROM FFD416 FFDC16 Interrupt vector area FFFE16 Reserved memory area FFFF16 Flash memory ID code Special page
FF0016 FFD416 FFDC16 FFFE16 FFFF16 Reserved memory area Special page
Fig. 7 Memory map diagram
Feb 18, 2005 page 9 of 85 REJ03B0122-0101
7512 Group
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 0FE016 0FE116 0FE216 0FE316 0FE416 0FE516 0FE616 0FE716 0FE816 0FE916 0FEA16 0FEB16 0FEC16 0FED16 0FEE16 0FEF16
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Discharge counter latch low-order register (DCHARGEL) Discharge counter latch high-order register (DCHARGEH) Charge counter latch low-order register (CHARGEL) Charge counter latch high-order register (CHARGEH) Current integrator control register (CINFCON) Short current detector control register (SCDCON) Over current detector control register (OCDCON) Current detect time set up register 1 (OCDTIME1) Wake up current detector control register1 (WUDCON1) Current detect status register (OCDSTS) Wake up current detector control register2 (WUDCON2) Serial I/O2 control register 1 (SIO2CON1) Serial I/O2 control register 2 (SIO2CON2) Serial I/O2 register (SIO2) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIOSTS) Serial I/O1 control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM) Flash memory control register 0 (FMCR0) Flash memory control register 1 (FMCR1) Flash memory control register 2 (FMCR2) Reserved * Reserved * Reserved * Reserved * Reserved * Reserved * Reserved * Reserved * Reserved * Reserved * Reserved * Reserved * Reserved *
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516
Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Timer count source selection register (TCSS) SFR protect control register (PRREG) I2C data shift register (S0) I2C address register (S0D) I2C status register (S1) I2C control register (S1D) I2C clock control register (S2) I2C start/stop condition control register (S2D) I2C additional register (S3) 32kHz RC oscillation control register0 (32KOSCC0) 32kHz RC oscillation control register1 (32KOSCC1) AD control register (ADCON) AD conversion low-order register (ADL) AD conversion high-order register (ADH) MISRG2 MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register 1 (INTEDGE1) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Charge over current detector control register (COCDCON) Current detect time set up register 2 (OCDTIME2) High-speed RC oscillator frequency set up register (O4RCFRG) High-speed RC oscillator frequency counter (O4RCFCNT) High-speed RC oscillator control register (O4RCCOT) Interrupt edge selection register 2 (INTEDG2)
* Reserved : Do not write any data to the reserved area.
Fig. 8 Memory map of special function register (SFR)
Feb 18, 2005 page 10 of 85 REJ03B0122-0101
7512 Group
I/O PORTS
The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that bit, that pin becomes an output pin.
If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.
Table 5 I/O port function Pin Name Port P0 P00/SIN2 P01/SOUT2 P02/SCLK2 __________ P03/SRDY2 P04/AN8 P05/AN9 P06/CFETCNT/AN10 Input/Output I/O Structure Non-Port Function Related SFRs Input/output, CMOS compatible input level Serial I/O2 function I/O Serial I/O2 control register individual bits CMOS 3-state output Ref.No. (1) (2) (3) (4) (5) (6) (7)
A/D conversion input A/D conversion input Over current detector output A/D conversion input PWM output CMOS compatible input level N-channel open-drain output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS/SMBUS input level (when selecting I2C-BUS interface function) N-channel open-drain output
P07/AN11/PWM1 P10-P17 P20/XCOUT P21/XCIN P22/SDA1 P23/SCL1 P24/SDA2/RxD P25/SCL2/TxD Port P1 Port P2
AD control register MISRG2 AD control register, MISRG2 Charge over current detect control register AD control register, MISRG2 PWM control register
(8) (9)
Sub-clock generating circuit I2C-BUS interface function I/O I2C-BUS interface function I/O Serial I/O1 function I/O
CPU mode register MISRG2 I2C control register I2C control register Serial I/O1 control register
(10) (11) (12) (13) (14) (15)
P26/SCLK P27/CNTR0/ __________ SRDY1 P30/AN0- P35/AN5 P40/CNTR1 P41/INT0 P42/INT1 P43/INT2/SCMP2
Port P3 Port P4
P44/INT3/PWM0
P45/DFETCNT
Serial I/O1 control register Serial I/O1 control register Timer XY mode register AD control register MISRG2 Timer Y function I/O Timer XY mode register External interrupt input Interrupt edge selection register 1 CMOS compatible input level External interrupt input Interrupt edge selection N-channel open-drain output SCMP2 output register 2 Serial I/O2 control register External interrupt input Interrupt edge selection PWM output register 2 PWM control register CMOS compatible input level Over current detector Short current detect control CMOS 3-state output output register Over current detect control register Wake up current detect control register
CMOS compatible input level Serial I/O1 function I/O CMOS 3-state output Serial I/O1 function I/O Timer X function I/O A/D conversion input
(16) (17) (6) (18) (19) (20)
(21)
(22)
Feb 18, 2005 page 11 of 85 REJ03B0122-0101
7512 Group
(1) Port P00
Direction register
(2) Port P01
P01/SOUT2 P-channel output disable bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit
Data bus
Port latch
Direction register
Data bus
Port latch
Serial I/O2 input
Serial I/O2 output
(3) Port P02
P02/SCLK2 P-channel output disable bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit
(4) Port P03
SRDY2 output enable bit Direction register
Direction register Data bus
Data bus
Port latch
Port latch
Serial I/O2 clock output Serial I/O2 external clock input
Serial I/O2 ready output
(5) Port P04
(6) Ports P05, P30-P35
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
A/D converter input Analog input pin selection bit
A/D converter input Analog input pin selection bit
(7)Port P06
Charge over current detector enable bit Direction register
(8)Port P07
PWM output pin selection bit PWM enable bit Direction register
Data bus
Port latch Data bus Port latch
1 CFETCNToutput INT3 input CFETCNT-INT3 OR output valid bit
A/D converter input
Analog input pin selection bit
PWM output A/D converter input Analog input pin selection bit
0 Charge FET control polarity switch bit
Fig. 9 Port block diagram (1)
Feb 18, 2005 page 12 of 85 REJ03B0122-0101
7512 Group
(9) Port P1
(10) Port P20
Port XC switch bit Direction register Data bus Direction register
Port latch
Data bus
Port latch
Port P21 32kHz RC Oscillation enable bit Port Xc switch bit 32kHz RC Oscillation enable bit Reference voltage
- +
(11) Port P21
(12) Port P22
I2C-BUS interface enable bit SDA/SCL pin selection bit Port XC switch bit Direction register Direction register
Data bus
Port latch
Data bus
Port latch
Sub-clock generating circuit input
SDA output SDA input
(13) Port P23
I2C-BUS interface enable bit SDA/SCL pin selection bit Direction register
(14) Port P24
I2C-BUS interface enable bit SDA/SCL pin selection bit Serial I/O1 enable bit Receive enable bit Direction register Data bus Port latch
Data bus
Port latch
SCL output SCL input
SDA output
SDA input Serial I/O1 input
(15) Port P25
Serial I/O1 enable bit Transmit enable bit I2C-BUS interface enable bit SDA/SCL pin selection bit
(16) Port P26
Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O1 output SCL output
SCL input
Serial I/O1 clock output Serial I/O1 external clock input
Fig. 10 Port block diagram (2)
Feb 18, 2005 page 13 of 85 REJ03B0122-0101
7512 Group
(17) Port P27
Pulse output mode
Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit
(18) Port P40
Direction register
Direction register Data bus Data bus Port latch Port latch
Pulse output mode Serial I/O1 ready output Timer output
CNTR0 interrupt input
Pulse output mode Timer output CNTR1 interrupt input
(19) Ports P41, P42
(20) Port P43
Serial I/O2 input/output comparison signal control bit
Direction register
Direction register
Data bus
Port latch Data bus Port latch
Interrupt input
Serial I/O2 input/output comparison signal output
INT2 interrupt input
(21) Port P44
PWM output pin selection bit PWM function enable bit Direction register
(22) Port P45
Charge over current detect enable bit Short current detect enable bit Over current detect enable bit Wake up current detect enable bit Direction register
Data bus
Port latch
Data bus
Port latch
PWM output DFETCNT output INT3 interrupt input INT2 input DFETCNT-INT2 OR output enable bit
1 0 Discharge FET control polarity switch bit
Fig. 11 Port block diagram (3)
Feb 18, 2005 page 14 of 85 REJ03B0122-0101
7512 Group
INTERRUPTS
Interrupts occur by 16 sources among 20 sources: seven external, twelve internal, and one software.
sNotes
When setting the followings, the interrupt request bit may be set to "1". *When switching external interrupt active edge Related register: Interrupt edge selection register 1 (address 003A16) I2C START/STOP condition control register (address 003016) Timer XY mode register (address 002316) *When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt edge selection register 1 (address 003A16) When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. (1) Set the corresponding interrupt enable bit to "0" (disabled). (2) Set the interrupt edge select bit or the interrupt source select bit. (3) Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. (4) Set the corresponding interrupt enable bit to "1" (enabled).
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The reset and the BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the reset and the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter.
Feb 18, 2005 page 15 of 85 REJ03B0122-0101
7512 Group
Table 6 Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 SCL, SDA INT1 INT2 INT3 6 Serial I/O2 I 2C Timer X Timer Y Timer 1 Timer 2 Serial I/O1 reception Serial I/O1 Transmission 13 Over current detection FFE516 FFE416 7 8 9 10 11 12 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFF316 FFF216 Priority 1 2 3 4 5 Vector Addresses (Note 1) High Low FFFD16 FFFC16 FFFB16 FFF916 FFF716 FFF516 FFFA16 FFF816 FFF616 FFF416 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of SCL or SDA input At detection of either rising or falling edge of INT1 input At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At completion of serial I/O2 data reception / transmission At completion of data transfer At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At completion of serial I/O1 data reception At completion of serial I/O1 transfer shift or when transmission buffer is empty At discharge short current is detected, at discharge over current is detected, at wake up current is detected, or at charge over current is detected. At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At completion of A/D conversion 16 Current integration BRK instruction 17 FFDD16 FFDC16 FFDF16 FFDE16 At end of current integration period, or at end of calibration At BRK instruction execution Valid when current integrator is selected Non-maskable software interrupt Valid when serial I/O1 is selected STP release timer underflow Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O2 is selected
Valid when serial I/O1 is selected Valid when discharge short current detector or discharge current detector, or wake up current detector, or charge over current detector is selected. External interrupt (active edge selectable) External interrupt (active edge selectable)
CNTR0 CNTR1 A/D converter
14 15
FFE316 FFE116
FFE216 FFE016
Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority.
Feb 18, 2005 page 16 of 85 REJ03B0122-0101
7512 Group
Interrupt request bit Interrupt enable bit
Interrupt disable flag (I)
BRK instruction Reset
Fig. 12 Interrupt control
Interrupt request
b7
b0 Interrupt edge selection register 1 (INTEDGE1 : address 003A16) INT0 active edge selection bit 0 : Falling edge active 1 : Rising edge active INT1 active edge selection bit 0 : Falling edge active 1 : Rising edge active Not used (returns "0" when read) Serial I/O2 / INT3 interrupt source bit 0 : INT3 interrupt selected 1 : Serial I/O2 interrupt selected Current integrate/A/D converter interrupt source bit 0 : AD converter interrupt selected 1 : Current integrate interrupt selected Over current detect / Serial I/O1 transmit interrupt source bit 0 : Serial I/O1 transmit interrupt selected 1 : Over current detect interrupt selected Not used (returns "0" when read)
b7
b0 Interrupt edge selection register 2 (INTEDGE2 : address 0FF516) INT2 falling edge active bit 0 : No operation 1 : Falling edge active INT2 rising edge active bit 0 : No operation 1 : Rising edge active INT3 falling edge active bit 0 : No operation 1 : Falling edge active INT3 rising edge active bit 0 : No operation 1 : Rising edge active Not used (returns "0" when read)
b7
b0
Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit SCL/SDA interrupt request bit INT1 interrupt request bit INT2 interrupt request bit INT3 / Serial I/O2 interrupt request bit I2C interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued
b7
b0
Interrupt request register 2 (IREQ2 : address 003D16) Timer 1 interrupt request bit Timer 2 interrupt request bit Serial I/O1 reception interrupt request bit Serial I/O1 transmit / Over current detect interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit AD converter /current integrate interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued
b7
b0
Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit SCL/SDA interrupt enable bit INT1 interrupt enable bit INT2 interrupt enable bit INT3 / Serial I/O2 interrupt enable bit I2C interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled
b7
b0
Interrupt control register 2 (ICON2 : address 003F16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O1 reception interrupt enable bit Serial I/O1 transmit / Over current detect interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit AD converter / current integrate interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit) 0 : Interrupts disabled 1 : Interrupts enabled
Fig. 13 Structure of interrupt-related registers
Feb 18, 2005 page 17 of 85 REJ03B0122-0101
7512 Group
TIMERS
The 7512 Group has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are count down. When the timer reaches "0016", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1".
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count source selection bit.
b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bit b1b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bit b5b4 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop
(2) Pulse Output Mode
The timer counts the count source selected by Timer count source selection bit. Whenever the contents of the timer reach "0016", the signal output from the CNTR0 (or CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge selection bit is "0", output begins at " H". If it is "1", output starts at "L". When using a timer in this mode, set the corresponding port P27 ( or port P40) direction register to output mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR0 or CNTR1 pin. When the CNTR0 (or CNTR1) active edge selection bit is "0", the rising edge of the CNTR0 (or CNTR1) pin is counted. When the CNTR0 (or CNTR1) active edge selection bit is "1", the falling edge of the CNTR0 (or CNTR1) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is "0", the timer counts the selected signals by the count source selection bit while the CNTR0 (or CNTR1) pin is at "H". If the CNTR0 (or CNTR1) active edge selection bit is "1", the timer counts it while the CNTR0 (or CNTR1) pin is at "L". The count can be stopped by setting "1" to the timer X (or timer Y) count stop bit in any mode. The corresponding interrupt request bit is set each time a timer underflows.
Fig. 14 Structure of timer XY mode register
b7
b0 Timer count source selection register (TCSS : address 002816) Timer X count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer 12 count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XCIN) Not used (returns "0" when read)
sNote
When switching the count source by the timer 12, X and Y count source bit, the value of timer count is altered in inconsiderable amount owing to generating of a thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer.
Fig. 15 Structure of timer count source selection register
Feb 18, 2005 page 18 of 85 REJ03B0122-0101
7512 Group
Data bus
f(XIN)/16 (f(XCIN)/16 at low-speed mode) f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Prescaler X latch (8)
Pulse width Timer X count source selection bit measurement Timer mode Pulse output mode mode Prescaler X (8) P27/CNTR0 CNTR0 active edge selection "0" bit "1" Event counter mode Timer X count stop bit
Timer X latch (8)
Timer X (8)
To timer X interrupt request bit
To CNTR0 interrupt request bit
CNTR0 active edge selection "1" bit "0"
Q Q
Toggle flip-flop T R Timer X latch write pulse Pulse output mode
Port P27 direction register
Port P27 latch Pulse output mode Data bus
f(XIN)/16 (f(XCIN)/16 at low-speed mode) f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit
Prescaler Y latch (8) Pulse width measurement mode Timer mode Pulse output mode Prescaler Y (8)
Timer Y latch (8)
Timer Y (8)
P40/CNTR1
CNTR1 active edge selection "0" bit "1"
To timer Y interrupt request bit
Event counter mode
Timer Y count stop bit To CNTR1 interrupt request bit Q Toggle flip-flop T Q R Timer Y latch write pulse Pulse output mode
CNTR1 active edge selection "1" bit "0"
Port P40 direction register Pulse output mode
Port P40 latch
Data bus
Prescaler 12 latch (8)
Timer 1 latch (8)
Timer 2 latch (8)
f(XIN)/16 (f(XCIN)/16 at low-speed mode) f(XCIN) Timer 12 count source selection bit
Prescaler 12 (8)
Timer 1 (8)
Timer 2 (8)
To timer 2 interrupt request bit To timer 1 interrupt request bit
Fig. 16 Block diagram of timer X, timer Y, timer 1, and timer 2
Feb 18, 2005 page 19 of 85 REJ03B0122-0101
7512 Group
SERIAL I/O1
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O1. A dedicated timer is also provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the serial I/O mode selection bit of the serial I/O1 control register (bit 6 of address 001A16) to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB.
Data bus Address 001816 Receive buffer register P24/RXD Receive shift register Shift clock Serial I/O1 control register Address 001A16
Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit
P26/SCLK Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1/4 Address 001C16 Clock control circuit Shift clock P25/TXD Transmit shift register Transmit buffer register Address 001816 Data bus Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916
XIN
BRG count source selection bit 1/4
P27/SRDY1
F/F
Falling-edge detector
Fig. 17 Block diagram of clock synchronous serial I/O1
Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Receive enable signal SRDY1 Write pulse to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection
TBE = 1 TSC = 0
Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" .
Fig. 18 Operation of clock synchronous serial I/O1 function
Feb 18, 2005 page 20 of 85 REJ03B0122-0101
7512 Group
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received.
Data bus Address 001816 OE P24/RXD
Receive buffer register
Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16
Character length selection bit ST detector 7 bits Receive shift register 8 bits PE FE SP detector
Clock control circuit Serial I/O1 synchronous clock selection bit P26/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 ST/SP/PA generator 1/16 P25/TXD Character length selection bit Transmit buffer register Address 001816 Data bus Transmit shift register
UART control register Address 001B16
XIN
Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916
Fig. 19 Block diagram of UART serial I/O1
Feb 18, 2005 page 21 of 85 REJ03B0122-0101
7512 Group
Transmit or receive clock
Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD TBE=0 TBE=1 TSC=1
ST
D0
D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s)
SP
ST
D0
D1
SP Generated at 2nd bit in 2-stop-bit mode
Receive buffer read signal
RBF=0 RBF=1 RBF=1
Serial input RXD
ST
D0
D1
SP
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1", can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 20 Operation of UART serial I/O1 function
[Transmit Buffer Register/Receive Buffer Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0".
Serial I/O1 Control Register (SIOCON)] 001A16
The serial I/O1 control register consists of eight control bits for the serial I/O1 function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P25/TXD pin.
[Serial I/O1 Status Register (SIOSTS)] 001916
The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1".
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
sNote
When using the serial I/O1, clear the I2C-BUS interface enable bit to "0" or the SCL/SDA pin selection bit to "0".
Feb 18, 2005 page 22 of 85 REJ03B0122-0101
7512 Group
b7
b0
Serial I/O1 status register (SIOSTS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read)
b7
b0
Serial I/O1 control register (SIOCON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O1 is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O1 is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P27 pin operates as ordinary I/O pin 1: P27 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P24 to P27 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P24 to P27 operate as serial I/O1 pins)
b7
b0
UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P25/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read)
Fig. 21 Structure of serial I/O1 control registers
sNotes
When setting the transmit enable bit to "1", the serial I/O1 transmit interrupt request bit is automatically set to "1". When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. (1) Set the serial I/O1 transmit interrupt enable bit to "0" (disabled). (2) Set the transmit enable bit to "1". (3) Set the serial I/O1 transmit interrupt request bit to "0" after 1 or more instructions have been executed. (4) Set the serial I/O1 transmit interrupt enable bit to "1" (enabled).
Feb 18, 2005 page 23 of 85 REJ03B0122-0101
7512 Group
qSerial I/O2
The serial I/O2 can be operated only as the clock synchronous type. As a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection bit (b6) of serial I/O2 control register 1. The internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selection bits (b2, b1, b0) of serial I/O2 control register 1. Regarding SOUT2 and SCLK2 being output pins, either CMOS output format or N-channel open-drain output format can be selected by the P01/SOUT2, P02/SCLK2 P-channel output disable bit (b7) of serial I/O2 control register 1. When the internal clock has been selected, a transfer starts by a write signal to the serial I/O2 register (address 001716). After completion of data transfer, the level of the SOUT2 pin goes to high impedance automatically but bit 7 of the serial I/O2 control register 2 is not set to "1" automatically. When the external clock has been selected, the contents of the serial I/O2 register is continuously sifted while transfer clocks are input. Accordingly, control the clock externally. Note that the SOUT2 pin does not go to high impedance after completion of data transfer. To cause the SOUT2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial I/O2 control register 2 to "1" when SCLK2 is "H" after completion of data transfer. After the next data transfer is started (the transfer clock falls), bit 7 of the serial I/O2 control register 2 is set to "0" and the SOUT2 pin is put into the active state. When the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred regardless of the internal clock to external clock, the serial I/O2 transmission/reception completion flag (Note) is set to "1" and the interrupt request bit is set to "1". The serial I/O2 transmission/reception completion flag is not automatically set to "0", even if the next transmission starts. In case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial I/O2 register becomes a fractional number of bits close to MSB if the transfer direction selection bit of serial I/O2 control register 1 is LSB first, or a fractional number of bits close to LSB if the said bit is MSB first. For the remaining bits, the previously received data is shifted. At transmit operation using the clock synchronous serial I/O, the SCMP2 signal can be output by comparing the state of the transmit pin SOUT2 with the state of the receive pin SIN2 in synchronization with a rise of the transfer clock. If the output level of the SOUT2 pin is equal to the input level to the SIN2 pin, "L" is output from the SCMP2 pin. If not, "H" is output. At this time, an INT2 interrupt request can also be generated. Select a valid edge by bit 2 of the interrupt edge selection register (address 003A16).
Note: After reset is released, the serial I/O2 transmission/reception completion flag is undefined. After the initial setting of serial I/O2 is completed, set this flag to "0".
b7 b0
Serial I/O2 control register 1 (SIO2CON1 : address 001516) Internal synchronous clock selection bits
b2 b1 b0
0 0 0 0 1 1
0 0 1 1 1 1
0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 0: f(XIN)/128 f(XCIN)/128 in low-speed mode) 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK2 output pin
SRDY2 output enable bit 0: P03 pin is normal I/O pin 1: P03 pin is SRDY2 output pin Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P01/SOUT2 ,P02/SCLK2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode )
b7 b0
Serial I/O2 control register 2 (SIO2CON2 : address 001616) Optional transfer bits
b2 b1 b0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0: 1 bit 1: 2 bit 0: 3 bit 1: 4 bit 0: 5 bit 1: 6 bit 0: 7 bit 1: 8 bit
Not used ( returns "0" when read) Serial I/O2 transmission reception completion flag 0: Transmission/reception not completed 1: Transmission/reception completed Serial I/O2 I/O comparison signal control bit 0: P43 I/O 1: SCMP2 output SOUT2 pin control bit (P01) 0: Output active 1: Output high-impedance
Fig. 22 Structure of Serial I/O2 control registers 1, 2
[Serial I/O2 Control Registers 1, 2] SIO2CON1 / SIO2CON2 The serial I/O2 control registers 1 and 2 are containing various selection bits for serial I/O2 control as shown in Figure 22.
Feb 18, 2005 page 24 of 85 REJ03B0122-0101
7512 Group
XCIN
Main clock division ratio selection bits (Note)
Divider
1/8 1/16 "10" "00" "01" 1/32 1/64 1/128 1/256
Internal synchronous clock selection bit
Data bus
XIN
P03 latch
"0" Serial I/O2 synchronous clock selection bit SRDY2 "1" SRDY2 output enable bit Synchronous circuit
SCLK2
P03/SRDY2
"1" "0"
External clock
P02 latch
"0"
Optional transfer bits (3) Serial I/O counter 2 (3) Serial I/O2 interrupt request
P02/SCLK2
"1" Serial I/O2 port selection bit
P01 latch
"0"
P01/SOUT2
"1" Serial I/O2 port selection bit
P00/SIN2
Serial I/O2 register (8)
P43 latch
"0"
P43/SCMP2/INT2
Q "1" Serial I/O2 I/O comparison signal control bit
D
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
Fig. 23 Block diagram of Serial I/O2
Transfer clock (Note 1) Write-in signal to serial I/O2 register
(Note 2)
Serial I/O2 output SOUT2 Serial I/O2 input SIN2
D0
D1
.
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected by setting bits 0 to 2 of serial I/O2 control register 1. 2: When the internal clock is selected as a transfer clock, the SCOUT2 pin has high impedance after transfer completion.
Fig. 24 Timing chart of Serial I/O2
Feb 18, 2005 page 25 of 85 REJ03B0122-0101
7512 Group
SCMP2 SCLK2 SOUT2 SIN2
Judgement of I/O data comparison
Fig. 25 SCMP2 output operation
Feb 18, 2005 page 26 of 85 REJ03B0122-0101
7512 Group
MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 26 shows a block diagram of the multi-master I2C-BUS interface and Table 7 lists the multi-master I 2 C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C address register, the I 2C data shift register, the I2C clock control register, the I2C control register, the I2C status register, the I2C start/stop condition control register and other control circuits. When using the multi-master I 2 C-BUS interface, set 1 MHz or more to .
Note: Renesas Technology Corporation assumes no responsibility for infringement of any third-party's rights or originating in the use of the connection control function between the I2C-BUS interface and the ports SCL1, SCL2, SDA1 and SDA2 with the bit 6 of I2C control register (002E16).
Table 7 Multi-master I2C-BUS interface functions Item Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at = 4 MHz)
Format
Communication mode
SCL clock frequency
System clock = f(XIN)/2 (high-speed mode) = f(XIN)/8 (middle-speed mode)
b7
I2C address register
b0 Interrupt generating circuit
Interrupt request signal (IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB
S0D Address comparator Serial data (SDA) Noise elimination circuit Data control circuit b7 I2C data shift register S0 b0 b7
b0
AL AAS AD0 LRB
MST TRX BB PIN SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0
AL circuit
S2D
I2C start/stop condition control register
S1
Internal data bus
I2C status register
b7
b0
ACS SCF WEB TOF TOM
BB circuit
S3
I2C additional register
Serial clock (SCL)
Noise elimination circuit
Clock control circuit
b7
ACK
b0
ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE
b7
TISS TSEL 10BIT SAD
b0
ALS ES0 BC2 BC1 BC0
S2 I2C clock control register
Clock division
S1D I 2 C control register
Operation status selection
System clock ()
Bit counter
Fig. 26 Block diagram of multi-master I2C-BUS interface
: Purchase of Renesas Technology Corporation's I2C components conveys a license under the Philips I2C Patent Rights to use these components an I2C system , provided that the system conforms to the I2C Standard Specification as defined by Philips.
Feb 18, 2005 page 27 of 85 REJ03B0122-0101
7512 Group
[I2C Data Shift Register (S0)] 002B16
The I2C data shift register (S0 : address 002B16) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted by one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted by one bit to the left. The minimum 2 machine cycles are required from the rising of the SCL clock until input to this register. The I2C data shift register is in a write enable status only when the I2C-BUS interface enable bit (ES0 bit : bit 3 of address 002E16) of the I2C control register is "1". The bit counter is reset by a write instruction to the I2C data shift register. When both the ES0 bit and the MST bit of the I2C status register (address 002D16) are "1", the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ES0 bit value.
b7 b0 I2C address register (S0D: address 002C16) Read/write bit Slave address
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB
Fig. 27 Structure of I2C address register
[I2C Address Register (S0D)] 002C16
The I 2C address register (address 002C16) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition is detected. *Bit 0: Read/write bit (RWB) This is not used in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RWB) of the I2C address register. The RWB bit is cleared to "0" automatically when the stop condition is detected. *Bits 1 to 7: Slave address (SAD0-SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode or the 10-bit addressing mode, the address data transmitted from the master is compared with these bit's contents.
Feb 18, 2005 page 28 of 85 REJ03B0122-0101
7512 Group
[I2C Clock Control Register (S2)] 002F16
The I2C clock control register (address 002F16) is used to set ACK control, SCL mode and SCL frequency. *Bits 0 to 4: SCL frequency control bits (CCR0-CCR4) These bits control the SCL frequency. Refer to Table 8. *Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to "0", the standard clock mode is selected. When the bit is set to "1", the high-speed clock mode is selected. When connecting the bus of the high-speed mode I2C bus standard (maximum 400 kbits/s), use 8 MHz or more oscillation frequency f(XIN) and 2 division clock. *Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock is generated. When this bit is set to "0", the ACK return mode is selected and SDA goes to "L" at the occurrence of an ACK clock. When the bit is set to "1", the ACK non-return mode is selected. The SDA is held in the "H" status at the occurrence of an ACK clock. However, when the slave address agree with the address data in the reception of address data at ACK BIT = "0", the SDA is automatically made "L" (ACK is returned). If there is a disagreement between the slave address and the address data, the SDA is automatically made "H" (ACK is not returned).
ACK clock: Clock for acknowledgment
b7
ACK
b0
ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE
I2C clock control register (S2 : address 002F16) SCL frequency control bits Refer to Table 8. SCL mode specification bit 0 : Standard clock mode 1 : High-speed clock mode ACK bit 0 : ACK is returned. 1 : ACK is not returned. ACK clock bit 0 : No ACK clock 1 : ACK clock
Fig. 28 Structure of I2C clock control register Table 8 Set values of I 2 C clock control register and SCL frequency Setting value of CCR4-CCR0 CCR4 CCR3 CCR2 CCR1 CCR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 SCL frequency (at = 4 MHz, unit : kHz) Standard clock High-speed clock mode mode Setting disabled Setting disabled Setting disabled - (Note 2) - (Note 2) 100 83.3 500/CCR value (Note 3) 17.2 16.6 16.1 Setting disabled Setting disabled Setting disabled 333 250 400 (Note 3) 166 1000/CCR value (Note 3) 34.5 33.3 32.3
*Bit 7: ACK clock bit (ACK) This bit specifies the mode of acknowledgment which is an acknowledgment response of data transfer. When this bit is set to "0", the no ACK clock mode is selected. In this case, no ACK clock occurs after data transmission. When the bit is set to "1", the ACK clock mode is selected and the master generates an ACK clock each completion of each 1-byte data transfer. The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (makes SDA "H") and receives the ACK bit generated by the data receiving device.
Note: Do not write data into the clock control register during transfer. If data is written during transfer, the I 2C clock generator is reset, so that data cannot be transferred normally. I2 C
...
...
...
...
0 1 1
1 1 1
1 1 1
1 1 1
Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected and CCR value = 5 (400 kHz, at = 4 MHz). "H" duration of the clock fluctuates from -4 to +2 machine cycles in the standard clock mode, and fluctuates from -2 to +2 machine cycles in the high-speed clock mode. In the case of negative fluctuation, the frequency does not increase because "L" duration is extended instead of "H" duration reduction. These are value when SCL clock synchronization by the synchronous function is not performed. CCR value is the decimal notation value of the SCL frequency control bits CCR4 to CCR0. 2: Each value of SCL frequency exceeds the limit at = 4 MHz or more. When using these setting value, use of 4 MHz or less. 3: The data formula of SCL frequency is described below: /(8 CCR value) Standard clock mode /(4 CCR value) High-speed clock mode (CCR value 5) /(2 CCR value) High-speed clock mode (CCR value = 5) Do not set 0 to 2 as CCR value regardless of frequency. Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0.
Feb 18, 2005 page 29 of 85 REJ03B0122-0101
...
1 0 1
7512 Group
[I2C Control Register (S1D)] 002E16
The I2C control register (address 002E16) controls data communication format. *Bits 0 to 2: Bit counter (BC0-BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. The I2C interrupt request signal occurs immediately after the number of count specified with these bits (ACK clock is added to the number of count when ACK clock is selected by ACK clock bit (bit 7 of address 002F16)) have been transferred, and BC0 to BC2 are returned to "0002". Also when a START condition is received, these bits become "0002" and the address data is always transmitted and received in 8 bits. *Bit 3: I2C interface enable bit (ES0) This bit enables to use the multi-master I2C-BUS interface. When this bit is set to "0", the use disable status is provided, so that the SDA and the SCL become high-impedance. When the bit is set to "1", use of the interface is enabled. When ES0 = "0", the following is performed. * PIN = "1", BB = "0" and AL = "0" are set (which are bits of the I2C status register at address 002D16 ). * Writing data to the I2C data shift register (address 002B16) is disabled. *Bit 4: Data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to "0", the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to "I 2C Status Register", bit 1) is received, transfer processing can be performed. When this bit is set to "1", the free data format is selected, so that slave addresses are not recognized. *Bit 5: Addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to "0", the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C address register (address 002C16) are compared with address data. When this bit is set to "1", the 10-bit addressing format is selected, and all the bits of the I 2C address register are compared with address data. *Bit 6: SDA/SCL pin selection bit This bit selects the input/output pins of SCL and SDA of the multimaster I2C-BUS interface. *Bit 7: I2C-BUS interface pin input level selection bit This bit selects the input level of the SCL and SDA pins of the multi-master I2C-BUS interface.
TSEL SCL1/P23 SCL SCL2/TxD/P25 Multi-master I2C-BUS interface TSEL TSEL SDA1/P22 SDA SDA2/RxD/P24 TSEL
Fig. 29 SDA/SCL pin selection bit
b7
TISS TSEL
10 BIT SAD
b0
ALS ES0 BC2 BC1 BC0
I2C control register (S1D : address 002E16) Bit counter (Number of transmit/receive bits) b2 b1 b0 0 0 0:8 0 0 1:7 0 1 0:6 0 1 1:5 1 0 0:4 1 0 1:3 1 1 0:2 1 1 1:1 I2C-BUS interface enable bit 0 : Disabled 1 : Enabled Data format selection bit 0 : Addressing format 1 : Free data format Addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format SDA/SCL pin selection bit 0 : Connect to ports P22, P23 1 : Connect to ports P24, P25 I2C-BUS interface pin input level selection bit 0 : CMOS input 1 : SMBUS input
Fig. 30 Structure of I2C control register
Feb 18, 2005 page 30 of 85 REJ03B0122-0101
7512 Group
[I2C Status Register (S1)] 002D16
The I2C status register (address 002D16) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. Set "00002" to the low-order 4 bits, because these bits become the reserved bits at writing. *Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to "0". If ACK is not returned, this bit is set to "1". Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from "1" to "0" by executing a write instruction to the I2C data shift register (address 002B16). *Bit 1: General call detecting flag (AD0) When the ALS bit is "0", this bit is set to "1" when a general call whose address data is all "0" is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to "0" by detecting the STOP condition or START condition, or reset.
General call: The master transmits the general call address "0016" to all slaves.
*Bit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data when the ALS bit is "0". (1)In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to "1" in one of the following conditions: * The address data immediately after occurrence of a START condition agrees with the slave address stored in the high-order 7 bits of the I2C address register (address 002C16). * A general call is received. (2)In the slave receive mode, when the 10-bit addressing format is selected, this bit is set to "1" with the following condition: * When the address data is compared with the I2C address register (8 bits consisting of slave address and RWB bit), the first bytes agree. (3)This bit is set to "0" by executing a write instruction to the I 2C data shift register (address 002B16) when ES0 is set to "1" or reset. *Bit 3: Arbitration lost detecting flag (AL) In the master transmission mode, when the SDA is made "L" by any other device, arbitration is judged to have been lost, so that this bit is set to "1". At the same time, the TRX bit is set to "0", so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to "0". The arbitration lost can be detected only in the master transmission mode. When arbitration is lost during slave address transmission, the TRX bit is set to "0" and the reception mode is set. Consequently, it becomes possible to detect the agreement of its own slave address and address data transmitted by another master device.
Arbitration lost :The status in which communication as a master is disabled.
*Bit 4: SCL pin low hold bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the PIN bit changes from "1" to "0". At the same time, an interrupt request signal occurs to the CPU. The PIN bit is set to "0" in synchronization with a falling of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the PIN bit. When the PIN bit is "0", the SCL is kept in the "0" state and clock generation is disabled. Figure 32 shows an interrupt request signal generating timing chart. The PIN bit is set to "1" in one of the following conditions: * Executing a write instruction to the I2 C data shift register (address 002B16). (This is the only condition which the prohibition of the internal clock is released and data can be communicated except for the start condition detection.) * When the ES0 bit is "0" * At reset * When writing "1" to the PIN bit by software The conditions in which the PIN bit is set to "0" are shown below: * Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) * Immediately after completion of 1-byte data reception * In the slave reception mode, with ALS = "0" and immediately after completion of slave address agreement or general call address reception * In the slave reception mode, with ALS = "1" and immediately after completion of address data reception *Bit 5: Bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to "0", this bus system is not busy and a START condition can be generated. The BB flag is set/reset by the SCL, SDA pins input signal regardless of master/slave. This flag is set to "1" by detecting the start condition, and is set to "0" by detecting the stop condition. The condition of these detecting is set by the start/stop condition setting bits (SSC4-SSC0) of the I2C start/stop condition control register (address 003016). When the ES0 bit of the I 2C control register (address 002E16) is "0" or reset, the BB flag is set to "0". For the writing function to the BB flag, refer to the sections "START Condition Generating Method" and "STOP Condition Generating Method" described later.
Feb 18, 2005 page 31 of 85 REJ03B0122-0101
7512 Group
*Bit 6: Communication mode specification bit (transfer direction specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is "0", the reception mode is selected and the data of a transmitting device is received. When the bit is "1", the transmission mode is selected and address data and control data are output onto the SDA in synchronization with the clock generated on the SCL. This bit is set/reset by software and hardware. About set/reset by hardware is described below. This bit is set to "1" by hardware when all the following conditions are satisfied: * When ALS is "0" * In the slave reception mode or the slave transmission mode * When the R/W bit reception is "1" This bit is set to "0" in one of the following conditions: * When arbitration lost is detected. * When a STOP condition is detected. * When writing "1" to this bit by software is invalid by the START condition duplication preventing function (Note). * With MST = "0" and when a START condition is detected. * With MST = "0" and when ACK non-return is detected. * At reset *Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is "0", the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is "1", the master is specified and a START condition and a STOP condition are generated. Additionally, the clocks required for data communication are generated on the SCL. This bit is set to "0" in one of the following conditions. * Immediately after completion of 1-byte data transfer when arbitration lost is detected * When a STOP condition is detected. * Writing "1" to this bit by software is invalid by the START condition duplication preventing function (Note). * At reset
Note: START condition duplication preventing function The MST, TRX, and BB bits is set to "1" at the same time after confirming that the BB flag is "0" in the procedure of a START condition occurrence. However, when a START condition by another master device occurs and the BB flag is set to "1" immediately after the contents of the BB flag is confirmed, the START condition duplication preventing function makes the writing to the MST and TRX bits invalid. The duplication preventing function becomes valid from the rising of the BB flag to reception completion of slave address.
b7
b0 I2C status register (S1 : address 002D16) Last receive bit (Note) 0 : Last bit = "0" 1 : Last bit = "1" General call detecting flag (Note) 0 : No general call detected 1 : General call detected Slave address comparison flag (Note) 0 : Address disagreement 1 : Address agreement Arbitration lost detecting flag (Note) 0 : Not detected 1 : Detected SCL pin low hold bit 0 : SCL pin low hold 1 : SCL pin low release Bus busy flag 0 : Bus free 1 : Bus busy Communication mode specification bits 00 : Slave receive mode 01 : Slave transmit mode 10 : Master receive mode 11 : Master transmit mode
MST TRX BB PIN AL AAS AD0 LRB
Note: These bits and flags can be read out, but cannot be written. Write "0" to these bits at writing.
Fig. 31 Structure of I2C status register
SCL PIN
IICIRQ
Fig. 32 Interrupt request signal generating timing
Feb 18, 2005 page 32 of 85 REJ03B0122-0101
7512 Group
START Condition Generating Method
When writing "1" to the MST, TRX, and BB bits of the I2C status register (address 002D16) at the same time after writing the slave address to the I2 C data shift register (address 002B16) with the condition in which the ES0 bit of the I2C control register (address 002E16) is "1" and the BB flag is "0", a START condition occurs. After that, the bit counter becomes "0002" and an SCL for 1 byte is output. The START condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 33, the START condition generating timing diagram, and Table 9, the START condition generating timing table.
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in Figures 35, 36, and Table 11. The START/STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be detected only when the input signal of the SCL and SDA pins satisfy three conditions: SCL release time, setup time, and hold time (see Table 11). The BB flag is set to "1" by detecting the START condition and is reset to "0" by detecting the STOP condition. The BB flag set/reset timing is different in the standard clock mode and the high-speed clock mode. Refer to Table 11, the BB flag set/ reset time.
Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal "IICIRQ" occurs to the CPU.
I2C status register write signal SCL SDA Setup time Hold time
SCL release time SCL SDA Setup time Hold time
BB flag set time
Fig. 33 START condition generating timing diagram
BB flag
Table 9 START condition generating timing table Standard clock mode High-speed clock mode Item 5.0 s (20 cycles) 2.5 s (10 cycles) Setup time 5.0 s (20 cycles) 2.5 s (10 cycles) Hold time
Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles.
Fig. 35 START condition detecting timing diagram
SCL release time SCL SDA BB flag Setup time Hold time
BB flag reset time
STOP Condition Generating Method
When the ES0 bit of the I2C control register (address 002E16) is "1", write "1" to the MST and TRX bits, and write "0" to the BB bit of the I2C status register (address 002D16) simultaneously. Then a STOP condition occurs. The STOP condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 34, the STOP condition generating timing diagram, and Table 10, the STOP condition generating timing table.
Fig. 36 STOP condition detecting timing diagram Table 11 START condition/STOP condition detecting conditions Standard clock mode High-speed clock mode SCL release time Setup time Hold time SSC value + 1 cycle (6.25 s) 4 cycles (1.0 s) SSC value + 1 cycle < 4.0 s (3.125 s) 2 cycles (1.0 s) 2 SSC value + 1 cycle < 4.0 s (3.125 s) 2 cycles (0.5 s) 2 SSC value -1 + 2 cycles (3.375 s) 3.5 cycles (0.875 s) 2
I2C status register write signal SCL SDA Setup time Hold time
BB flag set/ reset time
Note: Unit : Cycle number of system clock SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0. Do not set "0" or an odd number to SSC value. The value in parentheses is an example when the I2C START/ STOP condition control register is set to "1816" at = 4 MHz.
Fig. 34 STOP condition generating timing diagram Table 10 STOP condition generating timing table Standard clock mode High-speed clock mode Item 5.0 s (20 cycles) 3.0 s (12 cycles) Setup time 4.5 s (18 cycles) 2.5 s (10 cycles) Hold time
Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles.
Feb 18, 2005 page 33 of 85 REJ03B0122-0101
7512 Group
[I2C START/STOP Condition Control Register (S2D)] 003016
The I2C START/STOP condition control register (address 003016) controls START/STOP condition detection. *Bits 0 to 4: START/STOP condition set bits (SSC4-SSC0) SCL release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(XIN) because these time are measured by the internal system clock. Accordingly, set the proper value to the START/STOP condition set bits (SSC4 to SSC0) in considered of the system clock frequency. Refer to Table 11. Do not set "000002" or an odd number to the START/STOP condition set bit (SSC4 to SSC0). Refer to Table 12, the recommended set value to START/STOP condition set bits (SSC4-SSC0) for each oscillation frequency.
b7
b0
ARE SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0
I2C START/STOP condition control register (S2D : address 003016) START/STOP condition set bits SCL/SDA interrupt pin polarity selection bit 0 : Falling edge active 1 : Rising edge active SCL/SDA interrupt pin selection bit 0 : SDA valid 1 : SCL valid STP/Low speed mode data receive enable bit 0 : Disable 1 : Enable
*Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP) An interrupt can occur when detecting the falling or rising edge of the SCL or SDA pin. This bit selects the polarity of the SCL or SDA pin interrupt pin. *Bit 6: SCL/SDA interrupt pin selection bit (SIS) This bit selects the pin of which interrupt becomes valid between the SCL pin and the SDA pin. *Bit 7: STP/Low speed mode data receive enable bit Selecting this bit "1" enables I2C to receive the start condition address data even if the CPU is stopping or running at the low speed mode. The detecting the falling edge of the SDA pin, built-in RC oscillator begins oscillation, and receive the start condition address data. After receiving the last bit of address data ( in case of ACK clock bit ="1", after receiving ACK bit), SCL/SDA interrupt and I2C interrupt are requested at the same time. And then SCL pin becomes low hold state as a result of becoming SCL pin low hold bit "0". During this state, it is possible to start the Xin oscillation. And after oscillation becomes stable, normal I2C operation begins. If the start condition which is not satisfied the hold time of start condition is input, SCL/SDA interrupt is requested. In the low-speed mode, when this bit is set to "1", SCL/SDA interrupt which occur by the rising or falling edge of SCL or SDA is disabled.
Note: When changing the setting of the SCL/SDA interrupt pin polarity selection bit, the SCL/SDA interrupt pin selection bit, or the I 2C-BUS interface enable bit ES0, the SCL/SDA interrupt request bit may be set. When selecting the SCL/SDA interrupt source, disable the interrupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/ SDA interrupt pin selection bit, or the I 2C-BUS interface enable bit ES0 is set. Reset the request bit to "0" after setting these bits, and enable the interrupt.
Fig. 37 Structure of I2C START/STOP condition control register
Table 12 Recommended set value to START/STOP condition set bits (SSC4-SSC0) for each oscillation frequency Oscillation START/STOP Main clock System SCL release time Setup time frequency condition divide ratio clock (s) (s) f(XIN) (MHz) control register (MHz) 8 8 4 2 2 8 2 2 4 1 2 1 XXX11010 XXX11000 XXX00100 XXX01100 XXX01010 XXX00100 6.75 s (27 cycles) 6.25 s (25 cycles) 5.0 s (5 cycles) 6.5 s (13 cycles) 5.5 s (11 cycles) 5.0 s (5 cycles) 3.375 s (13.5 cycles) 3.125 s (12.5 cycles) 2.5 s (2.5 cycles) 3.25 s (6.5 cycles) 2.75 s (5.5 cycles) 2.5 s (2.5 cycles)
Hold time (s)
3.375 s (13.5 cycles) 3.125 s (12.5 cycles) 2.5 s (2.5 cycles) 3.25 s (6.5 cycles) 2.75 s (5.5 cycles) 2.5 s (2.5 cycles)
Note: Do not set "000002" or an odd number to the START/STOP condition set bits (SSC4 to SSC0).
Feb 18, 2005 page 34 of 85 REJ03B0122-0101
7512 Group
I2C additional register
(1) bit 0: Time-out mode bit (TOM) Setting the time-out mode bit "1" , continuity of I2C-Bus busy state for about 16ms (f(XIN)=4MHz, high-speed mode) makes time-out flag "1" and time-out interrupt occurs. Check the timeout flag to know which interrupt source of the SCL/SDA interrupt is occurred. When restart condition occurs in the middle of communication, the time-out timer is cleared. (2) bit 1: Time-out flag (TOF) Time-out flag becomes "1" when the time-out state occurs. Writing "1" to this bit, time-out timer is reset, and this bit is cleared "0" also. (3) I2C operation enable bit at WIT mode (WEB) This bit determines multi-master I2C-BUS interface operation at WIT mode. Setting this bit "0", multi-master I 2C interface source clock is not supplied at WIT mode. Setting this bit "1", multi-master I2C interface source clock is supplied even at WIT mode, and it makes possible multi-master I2C interface operation at WIT mode. Do not execute STP instruction at I 2 C operation enable bit at WIT mode is "1". (4) Stop condition flag (SCF) This flag turns to "1", when the stop condition is generated or detected. This bit is cleared "0" at reset, or when I2C-Bus interface enable bit is "0" or writing this bit "1". This bit is available only when I2C-Bus interface enable bit is "1". (5) ACK clock selection mode bit (ACS) Setting this bit "1" clears the ACK bit (bit 6 of 002F16) "0" and sets the ACK clock bit (bit 7 of 002F16) "1" automatically, when the stop condition is detected.
b7
ACS
b0
SCF WEB TOF TOM
I2C additional register (S3 : address 003116) Time-out mode bit 0 : Disable 1 : Enable Time-out flag 0 : Not generated 1 : Generated *Writing this bit "1", this flag is cleared I2C operation enable bit at WIT mode 0 : Disable 1 : Enable Stop condition flag 0 : Not detect stop condition 1 : Detect stop condition *Writing this bit "1", this flag is cleared ACK clock selection mode bit 0 : Disable 1 : Enable Not used (returns "0" when read)
Fig. 38 I2C additional register
Feb 18, 2005 page 35 of 85 REJ03B0122-0101
7512 Group
Address Data Communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats are described below. (1)7-bit addressing format To adapt the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 002E16) to "0". The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C address register (address 002C16). At the time of this comparison, address comparison of the RWB bit of the I 2C address register (address 002C16) is not performed. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 39, (1) and (2). (2)10-bit addressing format To adapt the 10-bit addressing format, set the 10BIT SAD bit of the I 2 C control register (address 002E16) to "1". An address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the I2C address register (address 002C16). At the time of this
comparison, an address comparison between the RWB bit of the I 2C address register (address 002C16) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the RWB bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is processed as an address data bit. When the first-byte address data agree with the slave address, the AAS bit of the I2C status register (address 002D16) is set to "1". After the second-byte address data is stored into the I 2C data shift register (address 002B16), perform an address comparison between the second-byte data and the slave address by software. When the address data of the 2 bytes agree with the slave address, set the RWB bit of the I2C address register (address 002C16) to "1" by software. This processing can make the 7-bit slave address and R/W data agree, which are received after a RESTART condition is detected, with the value of the I2C address register (address 002C16). For the data transmission format when the 10-bit addressing format is selected, refer to Figure 39, (3) and (4).
S
Slave address R/W 7 bits "0"
A
Data 1 to 8 bits
A
Data 1 to 8 bits
A/A
P
(1) A master-transmitter transnmits data to a slave-receiver S Slave address R/W 7 bits "1" A Data 1 to 8 bits A Data 1 to 8 bits A P
(2) A master-receiver receives data from a slave-transmitter Slave address R/W 1st 7 bits 7 bits "0" Slave address 2nd bytes 8 bits A/A
S
A
A
Data 1 to 8 bits
A
Data 1 to 8 bits
P
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address S Slave address R/W 1st 7 bits A Slave address 2nd bytes A Sr Slave address R/W 1st 7 bits A Data 1 to 8 bits A Data 1 to 8 bits A P
"1" 7 bits "0" 8 bits 7 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition A : ACK bit Sr : Restart condition
P : STOP condition R/W : Read/Write bit
: Master to slave : Slave to master
Fig. 39 Address data communication format
Feb 18, 2005 page 36 of 85 REJ03B0122-0101
7512 Group
Example of Master Transmission
An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. (1) Set a slave address in the high-order 7 bits of the I2C address register (address 002C16) and "0" into the RWB bit. (2) Set the ACK return mode and SCL = 100 kHz by setting "8516" in the I2C clock control register (address 002F16). (3) Set "0016" in the I2C status register (address 002D16) so that transmission/reception mode can become initializing condition. (4) Set a communication enable status by setting "0816" in the I2C control register (address 002E16). (5) Confirm the bus free condition by the BB flag of the I2C status register (address 002D16). (6) Set the address data of the destination of transmission in the high-order 7 bits of the I2C data shift register (address 002B16) and set "0" in the least significant bit. (7) Set "F016" in the I2C status register (address 002D16) to generate a START condition. At this time, a SCL for 1 byte and an ACK clock automatically occur. (8) Set transmit data in the I 2 C data shift register (address 002B16). At this time, a SCL and an ACK clock automatically occur. (9) When transmitting control data of more than 1 byte, repeat step (8). (10) Set "D016" in the I2C status register (address 002D16) to generate a STOP condition if ACK is not returned from slave reception side or transmission ends.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode and using the addressing format is shown below. (1) Set a slave address in the high-order 7 bits of the I2C address register (address 002C16) and "0" in the RWB bit. (2) Set the ACK non-return mode and SCL = 400 kHz by setting "2516" in the I2C clock control register (address 002F16). (3) Set "0016" in the I2C status register (address 002D16) so that transmission/reception mode can become initializing condition. (4) Set a communication enable status by setting "0816" in the I2C control register (address 002E16). (5) When a START condition is received, an address comparison is performed. (6) *When all transmitted addresses are "0" (general call): AD0 of the I2C status register (address 002D16) is set to "1" and an interrupt request signal occurs. *When the transmitted addresses agree with the address set in (1): ASS of the I2C status register (address 002D16) is set to "1" and an interrupt request signal occurs. * In the cases other than the above AD0 and AAS of the I2C status register (address 002D16) are set to "0" and no inter rupt request signal occurs. (7) Set dummy data in the I2C data shift register (address 002B16). (8) When receiving control data of more than 1 byte, repeat step (7). (9) When a STOP condition is detected, the communication ends.
Feb 18, 2005 page 37 of 85 REJ03B0122-0101
7512 Group
sPrecautions when using multi-master I2C-BUS interface
(1) Read-modify-write instruction The precautions when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master I2C-BUS interface are described below. * I2C data shift register (S0: address 002B16) When executing the read-modify-write instruction for this register during transfer, data may become a value not intended. * I2C address register (S0D: address 002C16) When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value not intended. It is because H/W changes the read/write bit (RWB) at the above timing. * I2C status register (S1: address 002D16) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by H/W. * I2C control register (S1D: address 002E16) When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte transfer, data may become a value not intended. Because H/W changes the bit counter (BC0-BC2) at the above timing. * I2C clock control register (S2: address 002F16) The read-modify-write instruction can be executed for this register. * I 2 C START/STOP condition control register (S2D: address 003016) The read-modify-write instruction can be executed for this register. (2) START condition generating procedure using multi-master 1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 5. : : LDA -- SEI BBS 5, S1, BUSBUSY BUSFREE: STA S0 LDM #$F0, S1 CLI : : BUSBUSY: CLI : : (Taking out of slave address value) (Interrupt disabled) (BB flag confirming and branch process) (Writing of slave address value) (Trigger of START condition generating) (Interrupt enabled)
* BB flag confirming * Writing of slave address value * Trigger of START condition generating When the condition of the BB flag is bus busy, enable interrupts immediately. (3) RESTART condition generating procedure 1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 4.) Execute the following procedure when the PIN bit is "0". : : LDM #$00, S1 LDA -- SEI STA S0 LDM #$F0, S1 CLI : : (Select slave receive mode) (Taking out of slave address value) (Interrupt disabled) (Writing of slave address value) (Trigger of RESTART condition generating) (Interrupt enabled)
2. Select the slave receive mode when the PIN bit is "0". Do not write "1" to the PIN bit. Neither "0" nor "1" is specified for the writing to the BB bit. The TRX bit becomes "0" and the SDA pin is released. 3. The SCL pin is released by writing the slave address value to the I2C data shift register. 4. Disable interrupts during the following two process steps: * Writing of slave address value * Trigger of RESTART condition generating (4) Writing to I2C status register Do not execute an instruction to set the PIN bit to "1" from "0" and an instruction to set the MST and TRX bits to "0" from "1" simultaneously. It is because it may enter the state that the SCL pin is released and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to "0" from "1" simultaneously when the PIN bit is "1". It is because it may become the same as above. (5) Process of after STOP condition generating Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes "0" after generating the STOP condition in the master mode. It is because the STOP condition waveform might not be normally generated. Reading to the above registers do not have the problem.
(Interrupt enabled)
2. Use "Branch on Bit Set" of "BBS 5, $002D, -" for the BB flag confirming and branch process. 3. Use "STA $2B, STX $2B" or "STY $2B" of the zero page addressing instruction for writing the slave address value to the I2C data shift register. 4. Execute the branch instruction of above 2 and the store instruction of above 3 continuously shown the above procedure example. 5. Disable interrupts during the following three process steps:
Feb 18, 2005 page 38 of 85 REJ03B0122-0101
7512 Group
PULSE WIDTH MODULATION (PWM)
The 7512 Group has a PWM function with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2.
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to "1", operation starts by initializing the PWM output circuit, and pulses are output starting at an "H". If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made.
Data Setting
The PWM output pin also functions as port P44 or port P07. The PWM output pin can be selected to either port P44/PWM0 or port P07/PWM1 by bit 2 (PWM output pin selectoin bit) of the PWM control register. Set the PWM period by the PWM prescaler, and set the "H" term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 (n+1) / f(XIN) = 63.75 (n+1) s (when f(XIN) = 4 MHz) Output pulse "H" term = PWM period m / 255 = 0.25 (n+1) m s (when f(XIN) = 4 MHz)
63.75 m (n+1) 255 PWM output
s
T = [63.75 (n+1)]
s
m: Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(XIN) = 4 MHz
Fig. 40 Timing of PWM period
Data bus
PWM prescaler pre-latch
PWM register pre-latch
Transfer control circuit
PWM prescaler latch Count source selection bit PWM prescaler "1"
PWM register latch
XIN
"0" 1/2
PWM register
PortP44/PWM0
Port P44 latch
PortP07/PWM1
Port P07 latch PWM enable bit PWM output pin selection bit
Fig. 41 Block diagram of PWM function
Feb 18, 2005 page 39 of 85 REJ03B0122-0101
7512 Group
b7
b0
PWM control register (PWMCON : address 001D16) PWM function enable bit 0: PWM disabled 1: PWM enabled Count source selection bit 0: f(XIN) 1: f(XIN)/2 PWM output pin selection bit 0: P44 1: P07 Not used (return "0" when read)
Fig. 42 Structure of PWM control register
A PWM output T PWM register write signal
B
C
B= C T2 T
T (Changes "H" term from "A" to "B".)
T2
PWM prescaler write signal
(Changes PWM period from "T" to "T2".)
When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change.
Fig. 43 PWM output timing when PWM register or PWM prescaler is changed
sNote
The PWM starts after the PWM enable bit is set to enable and "L" level is output from the PWM pin. The length of this "L" level output is as follows:
n+1 2 * f(XIN) n+1 f(XIN)
sec
(Count source selection bit = 0, where n is the value set in the prescaler)
sec
(Count source selection bit = 1, where n is the value set in the prescaler)
Feb 18, 2005 page 40 of 85 REJ03B0122-0101
7512 Group
A/D CONVERTER [AD Conversion Registers (ADL, ADH)] 003516, 003616
The AD conversion registers are read-only registers that store the result of an A/D conversion. Do not read these registers during an A/D conversion
b7
b0
AD control register (ADCON : address 003416) Analog input pin selection additional bit* 0 0 0 0 0 0 0 1 1 1 1 Analog input pin selection bits 0 0 0: P30/AN0 0 0 1: P31/AN1 0 1 0: P32/AN2 0 1 1: P33/AN3 1 0 0: P34/AN4 1 0 1: P35/AN5 1 1 1: Thermal sensor 0 0 0: P04/AN8 0 0 1: P05/AN9 0 1 0: P06/AN10 0 1 1: P07/AN11
[AD Control Register (ADCON)] 003416
The AD control register controls the A/D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 4 indicates the completion of an A/D conversion. The value of this bit remains at "0" during an A/D conversion and changes to "1" when an A/D conversion ends. Writing "0" to this bit starts the A/D conversion.
Not used (returns "0" when read) A/D conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (returns "0" when read) *Bit 0 of MISRG2 (003716)
Comparison Voltage Generator
The comparison voltage generator divides the voltage between AVSS and VREF into 1024 and outputs the divided voltages.
Channel Selector
The channel selector selects one of ports P04/AN8 to P07/AN11 and ports P30/AN0 to P35/AN5 and inputs the voltage to the comparator.
Fig. 44 Structure of AD control register
Comparator and Control Circuit
The comparator and control circuit compare an analog input voltage with the comparison voltage, and the result is stored in the AD conversion registers. When an A/D conversion is completed, the control circuit sets the A/D conversion completion bit and the A/D interrupt request bit to "1". Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A/D conversion. When the A/D converter is operated at low-speed mode, f(XIN) and f(XCIN) do not have the lower limit of frequency, because of the A/D converter has a built-in self-oscillation circuit.
10-bit reading (Read address 003616 before 003516)
b7
(Address 003616)
b7
b0 b9 b8 b0
(Address 003516)
b7 b6 b5 b4 b3 b2 b1 b0
Note : The high-order 6 bits of address 003616 become "0" at reading.
8-bit reading (Read only address 003516)
b7
(Address 003516)
b0 b9 b8 b7 b6 b5 b4 b3 b2
Easy thermal sensor
Easy thermal sensor detects voltage change of P-N diordes by thermal difference using A/D converter. Setting the Analog input pin selection additional bit "0" and Analog input pin selection bits "111" starts A/D conversion of thermal sensor.
Fig. 45 Structure of AD conversion registers
Data bus
AD control register (Address 003416)
b7
b0
Analog input pin selection additional bit
4 P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P35/AN5 P04/AN8 P05/AN9 P06/AN10 P07/AN11 A/D control circuit A/D interrupt request
Channel selector
Comparator
AD conversion high-order register (Address 003616) AD conversion low-order register (Address 003516) 10 Resistor ladder
VREF AVSS
Thermal sensor select signal
Fig. 46 Block diagram of A/D converter
Feb 18, 2005 page 41 of 85 REJ03B0122-0101
7512 Group
CURRENT INTEGRATOR
Current integrator integrates the current which flows through sense resistor connected between ISENS0 pin and ISENS1 pin. The current between sense resistor makes electrical potential difference between ISENS0 pin and ISENS1 pin, and it is integrated by the built-in integrator. The output of integrator is connected to comparator, and the integrator and comparator measures about 1mA current in case of using 10 m sense register. And charge/ discharge counter counts how many times the integrator overflows. Setting the current integrate enable bit "1", the current integrator starts the operation.
Current Integrate Mode
Setting the current integrate mode bit "0", input of the V-I converter is connected to the ISENS1 pin and ISENS0 pin, and the current integrator measures the electrical potential difference between ISENS1 pin and ISENS0 pin. The input voltage between ISENS1 and ISENS0 is converted to current by V-I converter, and input to the integrator.
The output of the integrator is connected to the comparator. The integrator integrates input voltage between ISENS1 pin and ISENS0 pin. And when output of the integrator amounts to compared voltage, output of the comparator rises "H", and charge(discharge) counter is increased 1 count. And at the same time, electric charge of the integrator's capacitor is discharged, then the integrator starts next integration. Charge(Dischrage) counter is counting the number of the times "H" output of the comparator during integration period(125msec), and at the end of the period, charge (discharge)counter is latched onto charge(discharge) counter latch. Then charge(discharge) counter is cleared "0", and starts new count. At the end of the period, current integrate interrupt occurs also. The current integrator has 2 set of comparator and counter for discharge and charge, and only discharge counter counts up in discharge state, and only charge counter counts up in charge state. The integrator and comparator are designed to sense approximate 1mA current, then 1 count of counter means approximate 1mA. Therefore reading the value of counter latch means measuring the total current which flows the sense resistor during integrate period(125msec).
Current integrate /AD converter interrupt source bit Edge detect Calibration control signal XCIN Integrator ISENS0 XX0 001 ISENS1 011 101 XX0 001 011 101 Current integrate control register
b2 b1 b0
AD conversion complete signal
Current integrate interrupt
125ms Timer
125ms over flow
V-I convertor
Charge counter
Charge counter latch
XX0 : Current integrate mode 001 : Zero calibration 011 : Full calibration for discharge 101 : Full calibration for charge
1.75V Discharge counter 1.50V 1.00V 0.75V Integrator coefficient selection bit 0.10V 0.05V Data Bus Discharge counter latch
Calibration current selection bit
Fig. 47 Block diagram of Current integrator
Feb 18, 2005 page 42 of 85 REJ03B0122-0101
7512 Group
Integrate period
125ms
Integrate period
125ms
ISENS1 input
V-I converter input
0V
1.75V
Integrator output
1.25V 0.75V
Discharge comparator Charge comparator
Discharge counter Discharge counter latch Charge counter Charge counter latch
n-6
n-5
n-4
n-3
n-2
n-1
n
0
1
2
3
Count value of last integrate period
m
n 1 3
0
2
Count value of last integrate period
m
ISENS1 input
V-I converter input
0V
1.75V
Integrator output
1.25V 0.75V
Discharge comparator
Discharge signal for the integrator
Discharge counter
n-3
n-2
n-1
Fig. 48 Current integrator timing diagram
Feb 18, 2005 page 43 of 85 REJ03B0122-0101
7512 Group
Calibration Mode
Setting the current integrate mode bit "1", the input of V-I converter is connected to internal AVSS or 0.05V or 0.1V for reference voltage. When the calibration selection bit is "00", both of plus and minus input of V-I converter are connected to internal AVSS, and zero calibration is operated. When the calibration selection bit is "01", plus input of V-I converter is connected to internal 0.05V or
0.1V reference voltage, and minus input of V-I converter is connected to internal AVSS, and then full calibration for discharge state is operated. When the calibration selection bit is "10", plus input of V-I converter is connected to internal AVSS, and minus input of V-I converter is connected to 0.05V or 0.1V reference voltage, and the full calibration for charge state is operated.
Integrate period 125ms
Integrate period 125ms
Integrate period 125ms
Integrate period 125ms
Calibration mode (Zero Calibration)
Calibration mode (Calibration for discharge state)
VINF input
Set the current integrate mode bit "1" and Calibration selection bit "00" Current integrate mode bit and Calibration selection bit
Set the calibration selection bit "01"
Set the current integrate mode bit "0"
XX0
001
011
XX0
Counter latch content flag
V-I converter input
0V
Integrator output
Discharge comparator Discharge counter Discharge counter latch
0
1
2
3
4
The result of calibration (Zero) The result of calibration (Discharge state)
Counter value of previous integrate period
Integrate period 125ms
Integrate period 125ms Zero Calibration
Integrate period 125ms Full calibration for discharge
1.75V Integrator output 1.25V 0.75V
V-I converter input 0V
Discharge comparator
Discharge signal for integrator
Discharge counter
n-1
n
0
3
4
0
1
2
3
4
5
6
Fig. 49 Calibration timing
Feb 18, 2005 page 44 of 85 REJ03B0122-0101
7512 Group
The calibration starts current integration for 125 ms, after discharging electric charge which remain in integrator's capacitor. After finished calibration period, value of the discharge(charge) counter is latched to discharge(charge) counter latch. At this time the current integrate interrupt occurs. Which interrupt has occurred current integrate interrupt for current integrate mode or for calibration mode can be judged by reading the counter latch content flag. The counter latch content flag shows the contents of counter latch, value for current integrate mode or value for calibration mode. Note that the contents of the counter latch is updated automatically at the end of next current integration or calibration. The calibration mode is continued until setting the current integrate mode bit "0".
sNote on using current integrate circuit
Just after setting the current integrate mode bit "1", discharge or charge counter may count up one in surplus, in the first integrate period, because of internal analog circuit still doesn't become stable in the first integrate period. This cause increase of one count on counting up counter or stopping counter in the first integrate period.
b7 b7 b6 b5 b4 b3 b2 b7
b0 b1 b0 b0 Discharge counter latch high-order register (000B16) Discharge counter latch low-order register (000A16)
b15 b14 b13 b12 b11 b10 b9 b8 b7 b7 b6 b5 b4 b3 b2 b7 b0 b1 b0 b0
Charge counter latch low-order register (000C16)
b15 b14 b13 b12 b11 b10 b9 b8
Charge counter latch high-order register (000D16)
b7
b0 Current integrate control register (000E16)
Current integrate mode bit 0 : Current integrate mode 1 : Calibration mode Calibration selection bit 00 : Zero calibration 01 : Full calibration for discharge 10 : Full calibration for charge 11 : Not used Calibration current selection bit (Note) 0 : 10A calibration 1 : 5A calibration Integrate coefficient selection bit 0 : 10m sense register 1 : 5m sense register Not used (Returns "0" when read) Counter latch contents flag 0 : Current integrate data 1 : Calibration data Current integrate enable bit 0 : Disable 1 : Enable
Note: This bit is protected.
Fig. 50 Current integrator registers
Feb 18, 2005 page 45 of 85 REJ03B0122-0101
7512 Group
OVER CURRENT DETECTOR
Over current detector detects the over current which flows through the sense resistor connected between ISENS1 pin and ISENS0 pin, and turn off the discharge control FET to stop battery from discharging or charging. In the low power state, and when current integrator disables, wake up current detector which detects approximate 1mA current and generates the interrupt is also built-in.
Wake Up Current Detector
Wake up current detector detects approximate 1A current with 10m sense resistor. Setting wake up current detect enable bit of the wake up current detect control register 1(001216) "1", wake up current detector starts the operation. The sensing voltage is 10 times amplified and compared by the comparator. The comparator is comparing every 3.9msec, and more than 1A current is keeping for about 62msec, wake up current detect flag(bit 0 of 001316) becomes "1", and the wake up current detect interrupt occurs. The enabling interrupt for wake up current detect is determined by wake up current detect interrupt enable bit(bit6 of 001216). Setting the wake up current detect restart bit "1" makes the wake up current detect state clear. The offset calibration of the amplifier and comparator is able to be adjusted by setting the wake up current compare voltage select bit. Setting the wake up current detect calibration enable bit(bit5 of 001416) "1", calibration mode starts. In the calibration mode, input of level shift circuit is connected to internal GND, and it is possible to measure the comparator threshold voltage at 0V input state, with setting wake up current detect compare voltage select bit. Then set the wake up current detect compare voltage select bit the value which is added comparator threshold voltage at 0V state and 0.1V(1A worth voltage).
Discharge Short Current Detector
Discharge short current detector detects the discharge short current(10A-47.5A) with 10m sense resistor. Setting discharge short current detect enable bit of the discharge short current detect control register(000F16) "1", discharge short current detector starts the operation. The compare voltage is determined by setting the discharge short current detect voltage select bit of the discharge short current detect control register, and the detect time is determined by setting the discharge short current detect time set up bit of the current detect time set up register 1(001116). The potential difference between sense resistor exceeds the compare voltage and continue more than detect time, then discharge short current detect flag(bit 2 of 001316) becomes "1", and discharge short current detect interrupt occurs. Enabling interrupt for discharge short current detect is determined by discharge short current interrupt enable bit(bit 4 of 000F16). And in case of the FET control enable bit is "1", The FET control signal is generated from DFETCNT pin with discharge short current interrupt. The polarity of the FET control signal is determined by setting the discharge FET control polarity switch bit(bit 5 of 000F16). Setting the discharge short current detect restart bit(bit 6 of 001316) "1" makes the discharge short current detect state clear.
Charge Over Current Detector
Charge over current detector detects the charge over current (10A-25A) with 10m sense resister. Setting charge over current detect enable bit of the charge over current detect control register (0FF016) "1", charge over current detector starts the operation. The compare voltage is determined by setting the charge over current detect voltage select bit of the charge over current detect control register (0FF016), and the detect time is determined by setting the charge over current detect time set up bit of the current detect time set up register 2 (0FF116). The potential difference between sense resister exceeds the compare voltage and continue more than detect time, then charge over current detect flag (bit 3 of 001316) becomes "1", and charge over current detect interrupt occurs. Enabling interrupt for charge over current detect is determined by charge over current interrupt enable bit. And in case of the charge FET control enable bit is "1", the charge FET control signal is generated from CFETCNT pin with charge over current interrupt. The polarity of the FET control signal is determined by setting the charge FET control polarity switch bit (bit 5 of 0FF016). Setting the charge over current detect restart bit (bit 7 of 001316) "1" makes the charge over current detect state clear.
Discharge Over Current Detector
Discharge over current detector detects the discharge over current(5A-20.5A) with 10m sense resistor. Setting discharge over current detect enable bit of the discharge over current detect control register(001016) "1", discharge over current detector starts the operation. The compare voltage is determined by setting the discharge over current detect voltage select bit of the discharge over current detect control register(001016), and the detect time is determined by setting the discharge over current detect time set up bit of the current detect time set up register 1(001116). The potential difference between sense resistor exceeds the compare voltage and continue more than detect time, then discharge over current detect flag(bit 1 of 001316) becomes "1", and discharge over current detect interrupt occurs. Enabling interrupt for discharge over current detect is determined by discharge over current interrupt enable bit. And in case of the discharge FET control enable bit is "1", the FET control signal is generated from DFETCNT pin with discharge over current interrupt. Setting the discharge overt current detect restart bit(bit5 of 001316) "1" makes the discharge over current detect state clear.
SFR Protect Control Register
SFR protect control register(002916), bit of MISRG2 (003716) and bit4,5 of MISRG (003816) protect SFR from changing the contents easily cause of like microcomputer runs away. When the bit of SFR protect control register bit of MISRG2, bit 4,5 of MISRG is "0", corresponded bit register is protected. Writing to the protected register, write "1" to the corresponded bit of protect register, then write the protected register in succession. If other register is written, the contents of SFR protect register is cleared "00".
Feb 18, 2005 page 46 of 85 REJ03B0122-0101
7512 Group
AVCC
Discharge short current detect voltage select bit Discharge over current detect voltage select bit Wake up current detect voltage select bit Charge over current detect voltage select bit
Over current detect status register
Current detect time set up resister 1
FET control enable bit (when short current detect enable)
ISENS1 Level shift circuit
Discharge short current detect time counter
S R
Q
FET control enable bit (when over current detect enable) FET control polarity switch bit
Discharge FET
Discharge over current detect time counter
S R
Q
X10
Wake up calibration enable bit
XCIN/128
Wake up current detect time counter
0 Level shift circuit 1
S R
Q
Current detect time set up resister 2
Charge FET control enable bit Charge over current detect time counter
Charge FET
Discharge FET control polarity switch bit
S R
Q
Over current detect interrupt
Fig. 51 Block diagram of Over current detector
Feb 18, 2005 page 47 of 85 REJ03B0122-0101
7512 Group
b7
b0 SFR protect control register (002916) PRCR Short current detect control register protect bit (000F16) 0 : Write disable 1 : Write enable Over current detect control register protect bit (001016) 0 : Write disable 1 : Write enable Current detect time set up register protect bit (001116) 0 : Write disable 1 : Write enable Wake up current detect control register 1 protect bit (001216) 0 : Write disable 1 : Write enable Over current detect status register protect bit (001316) 0 : Write disable 1 : Write enable Wake up current detect control register 2 protect bit (001416) 0 : Write disable 1 : Write enable MISRG2 protect bit (003716) 0 : Write disable 1 : Write enable CPU mode register protect bit (003B16) 0 : Write disable 1 : Write enable
b7
b0 Discharge short current detect control register protect bit (000F16)
Short current detect voltage select bit 0000 : 0.100V 1000 : 0.300V 0001 : 0.125V 1001 : 0.325V 0010 : 0.150V 1010 : 0.350V 0011 : 0.175V 1011 : 0.375V 0100 : 0.200V 1100 : 0.400V 0101 : 0.225V 1101 : 0.425V 0110 : 0.250V 1110 : 0.450V 0111 : 0.275V 1111 : 0.475V Discharge short current detect interrupt enable bit 0 : Disable 1 : Enable Discharge FETcontrol polarity switch bit 0 : active "L" output 1 : active "H" output Discharge FETcontrol enable bit (When short current detect enable) 0 : FET control disable 1 : FET control enable Discharge short current detect enable bit 0 : Disable 1 : Enable
Note : All bits are protected.
Note : Same bits in this register are not able to protect.
b7
b0 Discharge over current detect control register (001016)
b7
b0 Current detect time set up register 1 (001116)
Discharge short current detect voltage select bit 00000 : 0.050V 10000 : 0.130V 00001 : 0.055V 10001 : 0.135V 00010 : 0.060V 10010 : 0.140V 00011 : 0.065V 10011 : 0.145V 00100 : 0.070V 10100 : 0.150V 00101 : 0.075V 10101 : 0.155V 00110 : 0.080V 10110 : 0.160V 00111 : 0.085V 10111 : 0.165V 01000 : 0.090V 11000 : 0.170V 01001 : 0.095V 11001 : 0.175V 01010 : 0.100V 11010 : 0.180V 01011 : 0.105V 11011 : 0.185V 01100 : 0.110V 11100 : 0.190V 01101 : 0.115V 11101 : 0.195V 01110 : 0.120V 11110 : 0.200V 01111 : 0.125V 11111 : 0.205V Discharge over current detect interrupt enable bit 0 : Disable 1 : Enable Discharge FET control enable bit (When over current detect enable) 0 : FET control disable 1 : FET control enable Discharge over current detect enable bit 0 : Disable 1 : Enable
Discharge short current detect time set up bit 0000 : 0s 1000 : 488s 0001 : 61s 1001 : 549s 0010 : 122s 1010 : 610s 0011 : 183s 1011 : 671s 0100 : 244s 1100 : 732s 0101 : 305s 1101 : 793s 0110 : 366s 1110 : 854s 0111 : 427s 1111 : 915s Discharge over current detect time set up bit 0000 : 1.0ms 1000 : 17.0ms 0001 : 3.0ms 1001 : 19.0ms 0010 : 5.0ms 1010 : 21.0ms 0011 : 7.0ms 1011 : 23.0ms 0100 : 9.0ms 1100 : 25.0ms 0101 : 11.0ms 1101 : 27.0ms 0110 : 13.0ms 1110 : 29.0ms 0111 : 15.0ms 1111 : 31.0ms Note : All bits are protected.
Note : All bits are protected.
Fig. 52 Over current detector registers (1)
Feb 18, 2005 page 48 of 85 REJ03B0122-0101
7512 Group
b7
b0 Wake up current detect control register 1 (001216)
b7
b0 Over current detect status register(001316)
Wake up current detect compare voltage select bit Wake up current detect compare voltage select bit n b5 0 0 0 0 0 b4 0 1 1 1 1 b3 X 0 0 0 0 b2 X 0 0 0 0 b1 X 0 0 1 1 b0 X 0 1 0 1 Setting disabled 1.04 1.05 1.06 1.07 0.01n+0.88 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 1.48 1.49 1.50 1.51
Wake up current detect flag 0 : Not detected 1 : Detected Discharge over current detect flag 0 : Not detected 1 : Detected Discharge over current detect flag 0 : Not detected 1 : Detected Charge over current detect flag 0 : Not detected 1 : Detected Wake up current detect restart bit 0 : Invalid 1 : Restart Discharge over current detect restart bit 0 : Invalid 1 : Restart Discharge short current detect restart bit 0 : Invalid 1 : Restart Charge over current detect restart bit 0 : Invalid 1 : Restart Note : All bits are protected.
compare voltage (V)
Wake up current detect interrupt enable bit 0 : Disable 1 : Enable Wake up current detect enable bit 0 : Disable 1 : Enable Note : All bits are protected.
b7
b0 Wake up current detect control register 2 (001416)
b7
b0 Charge over current detect control register (0FF016)
Reserved (Do not write "1"to this bit) Not used (returns "0" when read) Wake up calibration enable bit 0 : Disable 1 : Enable Reserved (Do not write "1"to this bit) Not used (returns "0" when read) Note : All bits are protected.
Charge over current detect voltage select bit 0000 : 0.025V 1000 : 0.065V 0001 : 0.030V 1001 : 0.070V 0010 : 0.035V 1010 : 0.075V 0011 : 0.040V 1011 : 0.080V 0100 : 0.045V 1100 : 0.085V 0101 : 0.050V 1101 : 0.090V 0110 : 0.055V 1110 : 0.095V 0111 : 0.060V 1111 : 0.100V Charge over current detect interrupt enable bit 0 : Disable 1 : Enable Charge FET control polarity switch bit 0 : Active "L" output 1 : Active "H" output
b7
b0 Current detect time set up register 2 (0FF116)
Charge FET control enable bit 0 : FET control disable 1 : FET control enable Charge over current detect enable bit 0 : Disable 1 : Enable Note : All bits are protected. The SFR protect bit control bit is in MISRG register (address 003816).
Charge over current detect time set up bit 0000 : 1.0ms 1000 : 17.0ms 0001 : 3.0ms 1001 : 19.0ms 0010 : 5.0ms 1010 : 21.0ms 0011 : 7.0ms 1011 : 23.0ms 0100 : 9.0ms 1100 : 25.0ms 0101 : 11.0ms 1101 : 27.0ms 0110 : 13.0ms 1110 : 29.0ms 0111 : 15.0ms 1111 : 31.0ms DFETCNT-INT2 OR output enable bit 0 : Disable 1 : Enable INT2 polarity switch bit 0 : invert 1 : not invert CFETCNT-INT3 OR output enable bit 0 : Disable 1 : Enable INT3 polarity switch bit 0 : invert 1 : not invert Note : All bits are protected. The SFR protect bit control bit is in MISRG register (address 003816).
Fig. 53 Over current detector registers (2)
Feb 18, 2005 page 49 of 85 REJ03B0122-0101
7512 Group
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control register (address 003916) after resetting, the watchdog timer is in the stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 003916) and an internal reset occurs at an underflow of the watchdog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 003916) may be started before an underflow. When the watchdog timer control register (address 003916) is read, the values of the high-order 6 bits of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read. qInitial value of watchdog timer At reset or writing to the watchdog timer control register (address 003916), each watchdog timer H and L is set to "FF16".
qWatchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register (address 003916) permits selecting a watchdog timer H count source. When this bit is set to "0", the count source becomes the underflow signal of watchdog timer L. The detection time is set to 262.144 ms at f(XIN) = 4 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency. When this bit is set to "1", the count source becomes the signal divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case is set to 1024 s at f(XIN) = 4 MHz frequency and 128 ms at f(XCIN) = 32 kHz frequency. This bit is cleared to "0" after resetting. qOperation of STP instruction disable bit Bit 6 of the watchdog timer control register (address 003916) permits disabling the STP instruction when the watchdog timer is in operation. When this bit is "0", the STP instruction is enabled. When this bit is "1", the STP instruction is disabled, once the STP instruction is executed, an internal reset occurs. When this bit is set to "1", it cannot be rewritten to "0" by program. This bit is cleared to "0" after resetting.
XCIN "10" Main clock division ratio selection bits (Note) XIN
"FF16" is set when watchdog timer control register is written to. Watchdog timer L (8) 1/16
Data bus "FF16" is set when watchdog timer control register is written to.
"0" "1" Watchdog timer H (8)
"00" "01"
Watchdog timer H count source selection bit
STP instruction disable bit STP instruction Reset circuit Internal reset
RESET
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 54 Block diagram of Watchdog timer
b7
b0 Watchdog timer control register (WDTCON : address 003916)
Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16
Fig. 55 Structure of Watchdog timer control register
Feb 18, 2005 page 50 of 85 REJ03B0122-0101
7512 Group
RESET CIRCUIT
To reset the microcomputer, RESET pin must be held at an "L" level for 20 XIN cycles or more. Then the RESET pin is returned to an "H" level (the power source voltage must be between 2.45 V and 2.55 V, and the oscillation must be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.49 V for VCC of 2.45 V.
Poweron Power source voltage 0V Reset input voltage 0V (Note)
RESET
VCC
0.2VCC
Note : Reset release voltage ; Vcc=2.45 V
RESET
VCC Power source voltage detection circuit
Fig. 56 Reset circuit example
XIN
RESET Internal reset
Address
?
?
?
?
FFFC
FFFD
ADH,L
Reset address from the vector table.
Data
?
?
?
?
ADL
ADH
SYNC
XIN: 10.5 to 18.5 clock cycles Notes 1: The frequency relation of f(XIN) and f() is f(XIN)=8 * f(). 2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 57 Reset sequence
Feb 18, 2005 page 51 of 85 REJ03B0122-0101
7512 Group
Address Register contents (1) (2) (3) (4) (5) (6) (7) (8) (9) Port P0 direction register (P0D) Port P1 direction register (P1D) Port P2 direction register (P2D) Port P3 direction register (P3D) Port P4 direction register (P4D) Discharge counter latch low-order register (DCHARGEL) Discharge counter latch high-order register (DCHARGEH) Charge counter latch low-order register (CHARGEL) Charge counter latch high-order register (CHARGEH) 000116 000316 000516 000716 000916 000A16 000B16 000C16 000D16 000E16 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 (32) SFR protect control register (PRREG) (33) I2C address register (S0D) (34) I2C status register (S1) (35) I2C control register (S1D) (36) I2C clock control register (S2) (37) I2C start/stop condition control register (S2D) (38) I2C additional register (S3)
Address Register contents 002916 002C16 0016 0016
002D16 0 0 0 1 0 0 0 X 002E16 002F16 0016 0016
003016 0 0 0 X X X X X 003116 0016 0016 0016
(39) 32kHz oscillation circuit control register 0 (32KOSCC0) 003216 (40) 32kHz oscillation circuit control register 1 (32KOSCC1) 003316 (41) AD control register (ADCON) (42) MISRG2 (43) MISRG (44) Watchdog timer control register (WDTCON) (45) Interrupt edge selection register 1 (INTEDGE1) (46) CPU mode register (CPUM) (47) Interrupt request register 1 (IREQ1) (48) Interrupt request register 2 (IREQ2) (49) Interrupt control register 1 (ICON1) (50) Interrupt control register 2 (ICON2) (51) Flash memory control register 0 (FMCR0) (52) Flash memory control register 1 (FMCR1) (53) Flash memory control register 2 (FMCR2)
(10) Current integrator control register (CINFCON)
003416 0 0 0 1 0 0 0 0 003716 003816 0016 0016
(11) Discharge short current detector control register (DSCDCON) 000F16 (12) Discharge over current detector control register (DOCDCON) 001016 (13) Current detect time set up register 1 (OCDTIME1) (14) Wake up current detector control register 1 (WDDCON1) (15) Over current detect status register (OCDSTS) (16) Wake up current detector control register 2 (WDDCON2) (17) Serial I/O2 control register 1 (SI02CON1) (18) Serial I/O2 control register 2 (SI02CON2) (19) Serial I/O status register (SIOSTS) (20) Serial I/O control register (SIOCON) (21) UART control register (UARTCON) (22) PWM control register (PWMCON) (23) Prescaler 12 (PRE12) (24) Timer 1 (T1) (25) Timer 2 (T2) (26) Timer XY mode register (TM) (27) Prescaler X (PREX) (28) Timer X (TX) (29) Prescaler Y (PREY) (30) Timer Y (TY) (31) Timer count source select register (TCSS) 001116 001216 001316 001416 001516
003916 0 0 1 1 1 1 1 1 003A16 0016
003B16 0 1 1 0 0 0 0 0 003C16 003D16 003E16 003F16 0016 0016 0016 0016
001616 0 0 X 0 0 1 1 1 001916 1 0 0 0 0 0 0 0 001A16 0016
0FE016 0 0 0 0 0 0 0 1 0FE116 0 1 0 0 0 0 0 0 0FE216 0016 0016 0016 AB16
001B16 1 1 1 0 0 0 0 0 001D16 002016 002116 002216 002316 002416 002516 002616 002716 002816 0016 FF16 0116 0016 0016 FF16 FF16 FF16 FF16 0016
(54) Charge over current detect control register (COCDCON) 0FF016 (55) Current detect time set up register 2 (OCDTIME2) (56) High-speed RC oscillator frequency set up register
(O4RCFRG)
0FF116 0FF216
(57) High-speed RC oscillator control register (O4RCCOT) (58) Interrupt edge selection register 2 (INTEDGE2) (59) Processor status register (60) Program counter
0FF416 0 0 0 0 0 0 0 X 0FF516 (PS) (PCH) (PCL) 0016 XXXXX1XX
FFFD16 contents FFFC16 contents
Note : X indicates Not fixed .
Fig. 58 Internal status at reset
Feb 18, 2005 page 52 of 85 REJ03B0122-0101
7512 Group
CLOCK GENERATING CIRCUIT
The 7512Group has four built-in oscillation circuits. Built-in oscillation circuit about 4MHz oscillation, or an oscillation circuit can be formed by connecting a resonator between XIN and XOUT for high speed oscillation, and an oscillation circuit can be formed by connecting capacitor and resistor, or resonator between XCIN and XCOUT for low speed oscillation. The oscillation source (built-in oscillation or XIN-XOUT oscillation) can be controlled by setting clock source switch bit (CPU mode register) and high-speed RC oscillation stop bit (MISRG2) and XIN switching inhibit bit(MISREG2). Immediately after power on, only the built-in oscillation circuit starts oscillation. In case of using XIN-XOUT oscillation circuit, change the clock source bit after start the XIN-XOUT oscillation setting the main clock (XIN -XOUT) stop bit (CPU mode register). In case of not using XIN -XOUT oscillation circuit, XIN pin and XOUT pin must be open. Setting the XIN switching inhibit bit "1" (disable switch to XIN), clock source switch bit become invalid, and XIN-XOUT oscillation circuit becomes disabled since. When this bit is set to "1", it cannot be rewritten to "0" by program. Setting the port Xc switch bit (CPU mode register) "1", 32kHz RC oscillation circuit or XCIN-XCOUT oscillation circuit starts oscillation. The selection of 32kHz RC oscillation circuit or XcIN-XCOUT oscillation circuit is selected by 32kHz RC oscillation enable bit (MISRG2). In case of using external resonator, connect resonator to XIN pin and XOUT pin (XCIN pin and XCOUT pin). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip.(An external feed-back resistor may be needed depending on conditions.) However, an external feed-back resistor is needed between XCIN and XCOUT. After reset, XCIN and XCOUT pins function as I/O ports.
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to "1". When the main clock XIN is restarted (by setting the main clock stop bit to "0"), set sufficient time for oscillation to stabilize. The sub-clock XCIN-XCOUT oscillating circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate.
32kHz RC oscillation circuit
Setting the port Xc switch bit "1" after setting the 32kHz RC oscillation enable bit "1", the built-in 32kHz RC oscillation circuit starts oscillation. In case of using 32kHz RC oscillation circuit, connect 91k resistor between XCIN-XCOUT, and connect 100pF capacitor between XCIN and GND. Setting appropriate value to the 32kHz oscillation circuit control register0,1 it is possible to adjust the frequency error cause by evenness of resistor and capacitor value . The resistor ladder divided by 512 adjusts the frequency, and it makes possible about 50Hz step adjustment. The theoretical frequency is calculated as follow. 1 f32KRC = 2RCln(1+2R1/R2)
Calibration for High-speed RC oscillation circuit
Setting the high-speed RC oscillation circuit calibration enable bit "1", built-in counter starts count the clock which is divided the frequency of the high-speed RC oscillation output by 1/2 for four cycles period of 32kHz RC oscillation clock, and high-speed RC oscillation frequency can be measured. The built-in counter is 9bit counter and lower 8bit count value is stored in the high-speed RC oscillation circuit frequency counter (0FF316) and higher 1bit is stored in bit 0 of high-speed RC oscillation circuit control register (0FF416). Renewing the high-speed RC oscillation frequency set up register (0FF216), oscillation frequency is altered. High-speed RC oscillation circuit frequency may change cause of change of VCC or operating, temperature, but adjusting the high-speed oscillation frequency set up register by software, oscillating frequency can be kept fixed. After power on, built-in high-speed RC oscillation starts the oscillation at about 4MHZ.
Frequency Control (1) Middle-speed mode
The internal clock is the frequency of high-speed RC oscillation clock or XIN divided by 8. After reset, this mode is selected.
(2) High-speed mode
The internal clock is half the frequency of XIN.
(3) Low-speed mode
The internal clock is half the frequency of high-speed RC oscillation clock or XCIN.
sNote
If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after power on and at returning from the stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3*f(XCIN).
Feb 18, 2005 page 53 of 85 REJ03B0122-0101
7512 Group
100pF C XCIN
91k R XCOUT comparator 1/2 clock control circuit
32kHz oscillation circuit control register 0,1
Vcc 2 (1.25V)
35.84 70512 resistor ladder R1 R2
71.68k
Fig. 59 Block diagram of 32kHz RC oscillation circuit
b7
b0 32kHz oscillation control register 0 (003216)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b0 b8
32kHz oscillation control register 1 (003316)
Fig. 60 32kHz oscillation control register
b7
b0
b7 b6 b5 b4 b3 b2 b1 b0 b7 b0
High-speed RC oscillation frequency set up register (0FF216)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b0 b8
High-speed RC oscillation frequency counter (0FF316) (Note 1,2)
High-speed RC oscillation control register (0FF416) (Note 1,2) Bit8 of high-speed RC oscillation counter Not used (Returns "0" when read) High-speed RC oscillation calibration enable bit (Note 3) 0 : disable 1 : enable
Note 1 The first reading of high-speed RC oscillation frequency counter after enable high-speed RC oscillation calibration must be read after nine clock cycle of 32kHZ oscillation clock. Note 2 Read first 0FF316 and second 0FF416. Note 3 When high-speed RC oscillation calibration enable bit is "1", set up the clock source high-speed RC oscillation, and set up the main clock division ratio selection bits high-speed mode.
Fig. 61 High-speed RC oscillation register
Feb 18, 2005 page 54 of 85 REJ03B0122-0101
7512 Group
Oscillation Control (1) Stop mode
If the STP instruction is executed, the internal clock stops at an "H" level, and high-speed RC oscillation or XIN and XCIN oscillation stops. When the oscillation stabilizing time set after STP instruction released bit is "0", the prescaler 12 is set to "FF16" and timer 1 is set to "0116". When the oscillation stabilizing time set after STP instruction released bit is "1", set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. Either high-speed RC oscillation, XIN or XCIN divided by 16 is input to the prescaler 12 as count source. Oscillator restarts when an external interrupt is received, but the internal clock is not supplied to the CPU (remains at "H") until timer 1 underflows. The internal clock is supplied for the first time, when timer 1 underflows. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. When the oscillator is re____________ started by reset, apply "L" level to the RESET pin until the oscillation is stable since a wait time will not be generated. In case of using high-speed RC oscillation circuit as main clock, the oscillation stabilizing time does not almost need.
XCIN Rf CCIN XCOUT Rd CCOUT CIN COUT XIN XOUT
Rd (Note)
Notes : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between XIN and XOUT following the instruction.
Fig. 62 Ceramic resonator circuit
(2) Wait mode
If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator does not stop. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to "1" before executing of the STP or WIT instruction. When releasing the STP state, the prescaler 12 and timer 1 will start counting the clock high-speed RC oscillation, XIN divided by 16. Accordingly, set the timer 1 interrupt enable bit to "0" before executing the STP instruction.
XCIN Rf CCIN XCOUT Rd CCOUT XIN XOUT Open External oscillation circuit Vcc Vss
Fig. 63 External clock input circuit
sNote
When using the oscillation stabilizing time set after STP instruction released bit set to "1", evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12.
XCIN
XCOUT
XIN Open
XOUT Open
91k 100pF
Fig. 64 High-speed RC oscillation circuit and 32kHz RC oscillation circuit
Feb 18, 2005 page 55 of 85 REJ03B0122-0101
7512 Group
XCIN
XCOUT
Data bus
"1" "0"
Port XC switch bit 32kHZ RC oscillation enable bit Port XC switch bit 32kHZ RC oscillation enable bit XCIN-XOUT oscillation Port XC switch bit
32kHZ oscillation circuit control register 0, 1
XIN
(Note 3)
XOUT
Clock source switch bit XIN-XOUT oscillation
32kHZ RC oscillation Main clock division ratio selection bit (Note 1) Low-speed mode
1/2
1/2
High-speed RC oscillation High-speed or middle-speed mode
1/4
1/2
Prescaler 12 FF16
Timer 1 0116
Reset or STP instruction (Note 2)
High-speed RC oscillation circuit
XIN changing inhibit bit
Main clock division ratio selection bits (Note 1) Middle-speed mode
High-speed RC oscillation stop bit Main clock stop bit (XIN-XOUT)
High-speed or low-speed mode
Timing (Internal clock)
QS R
STP instruction WIT instruction
SQ R
QS R
STP instruction
Reset Interrupt disable flag l Interrupt request Note 1: Any one of high-speed mode, middle-speed mode or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port Xc switch bit (b1) to "1". 2: When the oscillation stabilizing time set after STP instruction release bit is "0". 3: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions.
Fig. 65 System clock generating circuit block diagram (Single-chip mode)
Feb 18, 2005 page 56 of 85 REJ03B0122-0101
7512 Group
sNotes on middle-speed mode switch set bit
When the middle-speed mode automatic switch set bit is set to "1" during operation in the low-speed mode, XIN oscillation starts automatically by detecting the rising edge or the falling edge of the SCL pin or the SDA pin and the microcomputer switch to the middle-speed mode. Select the timing which switches from the low-speed mode to the middle-speed mode by the middle-speed mode automatic switch wait time set bit. The timing is selectable from 4.5 to 5.5 cycles or 6.5 to 7.5 cycles in the low-speed mode. Select according to the oscillation start characteristic of the oscillator of XIN to be used. By writing "1" in the middle-speed mode automatic switch start bit during operation in the low-speed mode, XIN oscillation starts automatically and the microcomputer changes to the middle-speed mode.
b7
b0
b7
b0
MISRG(003816) Oscillation stabilizing time set after STP instruction released bit 0: Automatically set "0116" to Timer 1, FF16" to Prescaler 12 1: Automatically set nothing Middle-speed mode automatic switch set bit 0: Not set automatically 1: Automatic switching enable (Note1, 2) Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0: Invalid 1: Automatic switch start (Note2) Charge over current detect control register (0FF016) protect.bit 0:Write disable 1:Write enable Over current detect time set up register 2 (001416) protect bit 0:Write disable 1:Write enable Not used (returns "0" when read)
MISRG2(003716) Analog in additional bit bit0 ADCON bit2 bit1 bit0 (003416) 0 XXX 1 000 1 001 1 010 1 011 1 1XX
P35/AN5 - P30/AN0 P04/AN8 P05/AN9 P06/AN10 P07/AN11 Inhibit
32kHz RC oscillation calibration enable bit (Note 4) 0: Oscillating 1: Enable High-speed RC oscillation stop bit (Note4) 0: Oscillating 1: Stopping XIN switching inhibit bit (Note3, 4) 0: Enable switch to XIN 1: Disable switch to XIN 32kHz RC oscillation enable bit (Note4) 0: XCIN-XCOUT oscillation 1: 32kHz RC oscillation Serial I/O2 clock source selection bit (When low-speed mode) 0: XCIN 1: Built-in oscillator for SI/O2 Integrate coefficient selection bit of current integrate control register (000E16) protect bit 0: Write disable 1: Write enable Reserved (do not write "1")
Note 1: The microcomputer can be switched to the middle-speed mode automatically by the SCL/SDA interrupt during operation in the low-speed mode. Note 2: When switching from the low-speed mode to the middle-speed mode, the value of the CPU mode register also changes.
Note 3: When this bit is set to "1", it cannot be rewritten to "0" by program. Note 4: This bit is protected.
Fig. 66 Structure of MISRG1, MISRG2
Feb 18, 2005 page 57 of 85 REJ03B0122-0101
7512 Group
MISRG2 (bit 2) XIN oscillation
"1" RESET "0"
middle-speed mode(f()=500kHz) CM7=0 CM6=1 CM3 CM5=0(4MHz oscillating) "1" CM4=0(32kHz stopped) CM3=1 MISRG2(bit2)=0(High-speed RC oscillating)
"
"0"
"
"0"
"0"
"0"
"0
"
"0"
"1
CM " "0 6 CM " "1
"
"0 C" " 0 M6 "
4
"0"
"1 " "
CM4 "1"
CM4 "1"
CM4 "1"
CM4 "1"
CM4 "1"
C " 1 M4 C" " 1 M6 "0 "
CM4 "1"
"1
XIN oscillation XIN oscillation RC oscillation high-speed
XIN oscillation
CM6 "1" CM3 "1" CM5 "0" "0" "1" CM6 "1"
middle-speed mode(f()=500kHz) CM7=0 CM6=1 CM5=0(4MHz oscillating) CM4=1(32kHz oscillating) CM3=1 MISRG2(bit2)=1(High-speed RC oscillatin stopped) high-speed mode(f()=2MHz) CM7=0 CM6=0 CM5=0(4MHz oscillating) CM4=1(32kHz oscillating ) CM3=1 MISRG2(bit2)=0(High-speed RC oscillating) mode(f()=approximately 2MHz) CM7=0 CM6=0 CM5=1(4MHz oscillating stopped) CM4=1(32kHz oscillating ) CM3=0 MISRG2(bit2)=0(High-speed RC oscillating)
"0"
C " 1 M4 C" " 0 M6 "0 "
high-speed mode(f()=2MHz) CM7=0 MISRG2 (bit 2) CM6=0 "1" "0" CM5=0(4MHz oscillating) CM4=1(32kHz oscillating) CM3=1 MISRG2(bit2)=1(High-speed RC oscillating stopped)
RC oscillation high-speed mode(f()= approximately 2MHz) CM7=0 CM6=0 "0" CM5=0(4MHz oscillating) CM4=1(32kHz oscillating ) CM3=0 MISRG2(bit2)=0(High-speed RC oscillating)
RC oscillating middle-speed mode(f() =approximately 500kHz) CM7=0 CM6=1 CM5=1(4MHz oscillating stopped) CM4=1(32kHz oscillating) CM3=0 MISRG2(bit2)=0(High-speed RC oscillating)
CM5 "1"
"0"
RC oscillating middle-speed mode(f()= approximately 500kHz) CM7=0 CM6=1 CM5=0(4MHz oscillating) CM4=1(32kHz oscillating) CM3=0 MISRG2(bit2)=0(High-speed RC oscillating)
"1
"
6
"1
"
CM7 "1"
"
CM7 "1"
"0
"0"
CM "0 7 CM "
"0"
" "0 7 CM " " "1 "1 6 CM " "0
b2 MISRG2 (003716)
b7
b3 CPU mode register (003B16) CPUM
Low-speed mode(f()=16kHz) CM7=1 CM6=0 CM5=0(4MHz oscillating) CM4=1(32kHz oscillating) CM3=1 MISRG2(bit2)=1(High-speed RC oscillating stopped) Low-speed mode(f()=16kHz) CM7=1 CM6=0 CM5=1(4MHz oscillating stopped) CM4=1(32kHz oscillating) CM3=0 MISRG2(bit2)=0(High-speed RC oscillating)
"0"
CM5 "1"
Low-speed mode(f()=16MHz) CM7=1 CM6=0 CM5=1(4MHz oscillating stopped) CM4=1(32kHz oscillating) CM3=1 MISRG2(bit2)=1(High-speed RC oscillating stopped) XIN oscillation
Low-speed mode(f()=16kHz) CM7=1 CM6=0 CM5=1(4MHz oscillating stopped) CM4=1(32kHz oscillating) CM3=0 MISRG2(bit2)=1(High-speed RC oscillating stopped)
MISGR2 (bit2) "1" "0"
High-speed RC oscillation stop bit 0 : Oscillating 1 : Stopped
Clock source switch bit 0 : Built-in high-speed oscillating function 1 : XIN-XOUT oscillation function CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock(XIN- XOUT) stop bit 0 : oscillating 1 : stopped CM7,CM6: Main clock division ratio selection bits b7 b6 0 0 : f= f(XIN)/2 (high-speed mode) 0 1 : f= f(XIN)/8 (middle-speed mode) 1 0 : f= f(XCIN)/2 (low-speed mode) 1 1 : Not available
MISRG2 (bit 2) "1" "0"
middle-speed mode(f()=500kHz) CM3 CM7=0 "1" CM6=1 CM5=0(4MHz oscillating) CM4=1(32kHz oscillating) CM3=1 MISRG2(bit2)=0(High-speed RC oscillating)
"0"
Notes1 : 2: 3: 4: 5:
Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. Timer operates in the wait mode. When the stop mode is ended, a delay of approximately 2 ms occurs by connecting Timer 1 in middle/high-speed mode. When the stop mode is ended, the following is performed. (1) After the clock is restarted, a delay of approximately 32ms occurs in low-speed mode if Timer 12 count source selection bit is "0". (2) After the clock is restarted, a delay of approximately 250ms occurs in low-speed mode if Timer 12 count source selection bit is "1". 6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed mode. 7 : The example assumes that 4 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. indicates the internal clock. 8 : Use the 32 kHz RC oscillation enable bit (bit 4 in address 003716) to select XCIN-XCOUT oscillation or 32 kHz RC oscillation.
CM4 "1"
"0"
Feb 18, 2005 page 58 of 85 REJ03B0122-0101
"0"
XIN oscillation MISRG2 (bit 2)
XIN oscillation
XIN oscillation
CM6 "1" "1" "1" "0" "0" CM3 "1" "0" CM6 "1" CM5 "1"
Fig. 67 State transitions of system clock
high-speed mode(f()=2MHz) CM7=0 CM6=0 CM5=0(4MHz oscillating) CM4=0(32kHz stopped) CM3=1 MISRG2(bit2)=0(High-speed RC oscillating) RC oscillation high-speed mode(f()= approximately 2MHz) CM7=0 CM5 CM6=0 "0" CM5=0(4MHz oscillating) "0" CM4=0(32kHz stopped) CM3=0 MISRG2(bit2)=0(High-speed RC oscillating) RC oscillation high-speed mode(f()= approximately 2MHz) CM7=0 CM6=0 CM5=1(4MHz oscillating stopped) CM4=0(32kHz stopped) CM3=0 MISRG2(bit2)=0(High-speed RC oscillating) RC oscillating middle-speed mode(f()= approximately 500kHz) CM7=0 CM6=1 CM5=1(4MHz oscillating stopped) CM4=0(32kHz stopped) CM3=0 MISRG2(bit2)=0(High-speed RC oscillating) RC oscillating middle-speed mode(f()= approximately 500kHz) CM7=0 CM6=1 CM5=0(4MHz oscillating) CM4=0(32kHz stopped) CM3=0 MISRG2(bit2)=0(High-speed RC oscillating)
middle-speed mode(f()=500 kHz) CM7=0 CM6=1 CM5=0(4MHz oscillating) CM4=0(32kHz stopped) CM3=1 MISRG2(bit2)=1(High-speed RC oscillating stopped)
"0"
high-speed mode(f()=2MHz) CM7=0 CM6=0 CM5=0(4MHz oscillating) CM4=0(32kHz stopped) CM3=1 MISRG2(bit2)=1(High-speed RC oscillating stopped)
C M
4
"1
"
"0
"
7512 Group
FLASH MEMORY MODE
The 7512 Group (flash memory version) has flash memory that can be rewritten with a single power source. For this flash memory, two flash memory modes are available in which to read, program, and erase: the parallel I/O mode in which the flash memory can be manipulated using a programmer and the CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU).
Summary
Table 13 lists the summary of the 7512 Group (flash memory version). The flash memory of the 7512 Group is divided into 4 blocks of User ROM area and Boot ROM area as shown in Figure 68. In addition to the ordinary User ROM area to store the MCU operation control program, the flash memory has a Boot ROM area that is used to store a control program in a Boot mode. The user can write a rewrite control program in this Boot ROM area that suits the user's application system. This Boot ROM area can be rewritten in only parallel I/O mode.
Table 13 Summary of the 7512 Group (flash memory version) Item Power source voltage Program / Erase voltage Flash memory mode Erase block division User ROM area Boot ROM area Program method Erase method Program/Erase control method Number of commands Number of program/ Block 0 to Block 3 Erase times ROM code protection Block A, Block B Vcc = 2.5V2% Vcc = 2.5V2%
Specifications
2 modes (Parallel I/O mode, CPU rewrite mode) Refer to the Figure 68 1 block (4K bytes) (Note 1) Byte program Batch erasing Program/Erase control by software command 5 commands 100 times 1K times Available in parallel I/O mode
Note 1: This Boot ROM area can be rewritten in only parallel I/O mode.
Feb 18, 2005 page 59 of 85 REJ03B0122-0101
7512 Group
(1) CPU Rewrite Mode
In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the User ROM area shown in Figure 68 can be rewritten; the Boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the User ROM area and each block area. The control program for CPU rewrite mode can be stored in either User ROM or Boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area to be executed before it can be executed.
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I/O mode beforehand. See Figure 68 for details about the Boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the User ROM area. When the microcomputer is reset by pulling the P24/SDA2/RXD pin high, the CNVss pin high, the CPU starts operating using the control program in the Boot ROM area (program start address is FFFC16, FFFD16 fixation). This mode is called the "Boot" mode.
Block Address
Block addresses refer to the maximum address of each block. These addresses are used in the block erase command.
000016 User ROM area SFR area 004016 RAM 063F16 3FFF16 400016 Block 3 : 16K Byte 0FE016 SFR area 0FFF16 100016 C00016 Internal flash memory area (52K Byte) E00016 Block 0 : 8K Byte FFFF16 FFFF16 FFFF16 Block 1 : 8K Byte F00016 Boot ROM area 4K Byte 800016 Block 2 : 16K Byte
Notes 1: The Boot ROM area can be rewritten in only parallel input/output mode. (Access to any other areas is inhibited.) 2: To specify a block, use the maximum address in the block.
100016 Data block B : 2K Byte 180016 Data block A : 2K Byte 200016 Not used
Internal RAM area (1.5K Byte)
Fig. 68 Block diagram of built-in flash memory (M37512FCHP)
Feb 18, 2005 page 60 of 85 REJ03B0122-0101
7512 Group
Table 14 The difference between EW0 mode and EW1 mode Items EW0 mode Processor mode Single-chip mode Program area for rewrite control program User ROM area Operating area for rewrite control program Rewrite program in the flash memory area must be transfered from another area than flash memory area (ex. RAM area) and executed. Rewritable area User ROM area Restriction of software command Nothing EW1 mode Single-chip mode User ROM area Rewrite program can be executed in the User ROM area. (Note 3) User ROM area except rewrite program existing block and interrupt vector area (Note 1) *Program, Block erase command Command execution for block existing rewrite program is prohibited. * Read status register command execution is prohibited Read array mode Hold state (I/O port is kept the execution previous state.)
_____
The mode after program or erase CPU status at program and erase state How to detect the flash memory status
Read status register mode Executing
_____
The condition for shift to erase suspend status (Note 2)
*Read the RY/BY status flag, program status flag, erase status flag of the flash memory control register 0 on program. *Read the SR7, SR5, SR4 of the status register after execute the read status command Write "1" to the erase suspend enable bit and erase suspend requirement bit of the flash memory control register on program.
*Read the RY/BY status flag, program status flag, erase status flag of the flash memory control register 0 on program.
Write "1" to the erase suspend enable bit of the flash memory control register 1 on program and then interrupt request which is enabled occurred.
Note 1 Write "1" to the 8KB userblock E/W prohibit bit of the flash memory control register 1, rewrite operation on block 0, block 1 is enabled. Note 2 The enable time for reading flash memory after shifting to erase suspend status is max td(SR-ES). Note 3 Do not execute rewrite program on RAM area. (Do not execute program on RAM area whether rewrite control program or application program.)
qEW0 mode Setting "1" to CPU rewrite mode selection bit of flash memory control register 0, CPU rewrite mode starts, and software command becomes available. At this time, EW1 mode selection bit of the flash memory control register 1 becomes "0" (EW0 mode). For CPU rewrite mode select bit to be set to "1", it is necessary to write "0" and then "1" in succession. Program or erase operation is controlled by software command. The state of program or erase end can be checked by reading the flash memory control register or status register. In case of changing to the erase suspend mode during the erase operation, set the erase suspend enable bit to "1", and set the erase suspend request bit "1". And wait td(SR-ES). The user ROM area can be accessed after checking the erase suspend flag becomes "1". Setting the erase suspend request bit "0"(Erase restart), erase operation restarts.
qEW1 mode Setting the EW1 mode selection bit "1" (write "0" and then "1" in succession) after setting the CPU rewrite mode selection bit "1" (write "0" and then "1" in succession), the EW1 mode starts. The state of the program or erase end can be checked by reading the flash memory control register 0. Do not execute the software command of the read status register in the EW1 mode. Changing the erase suspend function to effective state, execute the block erase command after setting erase suspend enable bit "1". And the interrupt which triggers off shifting to erase suspend state must be enabled. td(SR-ES) later after interrupt request, erase sequence shift to erase suspend state, and interrupt is accepted. When the interrupt request occurs, erase suspend request bit becomes "1" automatically, and erase operation is suspended. In case of the erase operation is not completed (RY/BY status flag is "0") after interrupt routine ends, setting the erase suspend request bit "0", and execute the block erase command again.
Feb 18, 2005 page 61 of 85 REJ03B0122-0101
7512 Group
Outline Performance (CPU Rewrite Mode)
CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten in CPU rewrite mode. In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory by executing software commands. This rewrite control program must be transferred to the RAM before it can be executed. The MCU enters CPU rewrite mode by setting "1" to the CPU Rewrite Mode Select Bit (bit 1 of address 0FE016). Software commands are accepted once the mode is entered. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 69 shows the flash memory control register 0. Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is "0" (busy). Otherwise, it is "1" (ready). Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to "1", the MCU enters CPU rewrite mode. Software commands are accepted once the mode is entered. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly.
Therefore, use the control program in the RAM for write to bit 1. To set this bit to "1", it is necessary to write "0" and then write "1" in succession. The bit can be set to "0" by only writing "0". Bit 2 is 8KB user block E/W enable bit. Setting this bit and bit 4 (All user block E/W enable bit) of the flash memory control register 2 (0FE216) according to the table T-3, E/W protect is done at CPU Rewrite mode for User block Bit 3 is the flash memory reset bit used to reset the control circuit of internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU Rewrite Mode Select Bit is "1", setting "1" for this bit resets the control circuit. To release the reset, it is necessary to set this bit to "0". Bit 5 is User ROM area selection bit, and this bit is only available in Boot mode. Setting this bit "1", User ROM area can be accessed, and CPU rewrite is available. Bit 6 is the program status flag, and this flag changes "1" when flash memory write operation ends at abnormal state. If program error occurs, corresponding block is not available. Bit 7 is the erase status flag, and this flag changes "1" when flash memory erase operation ends at abnormal state. If erase error occurs, corresponding block is not available.
b7
b0
Flash memory control register 0 (address 0FE016) FMCR0
RY/BY status flag 0: Busy (being programmed or erased) 1: Ready CPU rewrite mode select bit (Note 1) 0: Normal mode 1: CPU rewrite mode 8 KB user block E/W enable bit (UBEWEN) (Note 1, 2) 0: E/W disable 1: E/W enable Flash memory reset bit (Note 3,4) 0: Normal operation 1: Reset
Not used ("0" at write)
User ROM area selection bit (Note 5) 0: Boot ROM area accessed 1: User ROM area accessed Program status flag 0: Passed 1: Error Erase status flag 0: Passed 1: Error Notes 1: For this bit to be set to "1", the user needs to write "0" and then "1" to it in succession. To reset this bit "0", only write "0". 2: This bit is valid when the CPU rewrite mode select bit is "1". 3: This bit is valid when the CPU rewrite mode select bit is "1". Fix this bit "0" when the CPU rewrite mode select bit is "0". 4: Setting this bit "1" (Resetting the flash memory control circuit), access to the flash memory is disabled for 10 sec. 5: Writing this bit must be executed in the RAM.
Fig. 69 Structure of flash memory control register
Feb 18, 2005 page 62 of 85 REJ03B0122-0101
7512 Group
Figure 70 shows the flash memory control register 1. Bit 0 is erase suspend enable bit, and setting this bit "1" erase suspend mode which makes erase operation interrupt briefly during erase operation. To set this bit to "1", it is necessary to write "0" and then write "1" in succession. This bit can be set to "0" by only writing "0". Bit 1 is erase suspend request bit. Writing this bit "1" when the
erase suspend enable bit is "1", erase operation is interrupted. Bit 6 is erase suspend flag, and becomes "0" during erase operation. Figure 71 shows flash memory control register 2. Bit 1 is EW1 mode select bit. Setting this bit "1", EW1 mode becomes available. Bit 4 is All user block E/W enable bit.
b7
b0
Flash memory control register 1 (0FE116, Initial 4016) FMCR1 Erase suspend enable bit (Note 1) 0 : Erase suspend invalid 1 : Erase suspend valid Erase suspend request bit (Note 2) 0 : Resume erase operation (No request) 1 : Interrupt erase operation (Requested) Not used ("0" at write) Erase suspend flag 0 : Executing erase operation 1 : Suspending erase operation (Erase suspend mode) Not used ("0" at write) Note 1 To set this bit "1", write "0" and then write "1" in succession. To reset this bit "0", only write "0". 2 This bit is valid only when erase suspend enable bit is "1".
Fig. 70 Structure of flash memory control register 1
b7
b0
Flash memory control register 2 (0FE216, Initial 4516) FMCR2 Reserved (returns unknown when read) EW1 mode select bit (Note 1, 3) 0 : E/W0 mode 1 : E/W1 mode Reserved (returns unknown when read) All user block E/W enable bit (Note 1, 2) 0 : E/W prohibit 1 : E/W enable Reserved ("0" at write, returns "0" at read) Not used (Indefinite at read) Not used (returns "0" at read) Note 1 To set this bit "1", it is necessary to write "0" and then write "1" in succession. This bit can be set to "0" by only writing "0". Note 2 This bit can be written only CPU rewrite mode selection bit "1". Note 3 Setting this bit "1" must be done at CPU rewrite mode select bit is "1".
Fig. 71 Structure of flash memory control register 2 Table. 15 Specification of E/W protect All user block E/W enable bit 0 0 1 1 8KB user block E/W enable bit 0 1 0 1 8 KBX2 block 16 KBX2 block Data block Addresses C00016 to FFFF16 Addresses 400016 to BFFF16 Addresses 100016 to 1FFF16 Protect Protect Protect Enable Protect Protect Enable Enable Enable Enable Enable Enable
Feb 18, 2005 page 63 of 85 REJ03B0122-0101
7512 Group
Figure 72 shows a flowchart for setting/releasing CPU rewrite mode.
E/W0 mode
Start
E/W1 mode
Start
Single-chip mode or Boot mode
Single-chip mode or Boot mode
Set CPU mode register (Note 1)
Set CPU mode register (Note 1)
Transfer CPU rewrite mode control program to RAM
Set CPU rewrite mode select bit to "1" (by writing "0" and then "1" in succession)
Jump to control program transferred in RAM (Subsequent operations are executed by control program in this RAM)
Set All user block E/W enable bit "1" (by writing "0" and then "1" in succession) Set 8KB user block E/W enable bit (writing "0" in case of E/W prohibit, writing "0" and then "1" in succession, in case of E/W enable)
Set CPU rewrite mode select bit to "1" (by writing "0" and then "1" in succession) Set E/W1 mode select bit = "1" (by writing "0" and then "1" in succession) Set All user block E/W enable bit "1" (by writing "0" and then "1" in succession) Set 8KB user block E/W enable bit (writing "0" in case of E/W prohibit, writing "0" and then "1" in succession, in case of E/W enable)
Check CPU rewrite mode entry flag
Using software command execute erase program, or other operation Check CPU rewrite mode entry flag Execute read array command (Note 2) Using software command execute erase, program, or other operation Set All user block E/W enable bit = "0" Set 8KB user block E/W enable bit = "0" Execute read array command (Note 2) Write "0" to CPU rewrite mode select bit Set All user block E/W enable bit = "0" Set 8KB user block E/W enable bit = "0" End Write "0" to CPU rewrite mode select bit
End
Notes 1: Set bits 6, 7 (main clock division ratio selection bits) at CPU mode register (003B16). 2: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array command.
Fig. 72 CPU rewrite mode set/release flowchart
Feb 18, 2005 page 64 of 85 REJ03B0122-0101
7512 Group
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.
(1) Operation speed
During CPU rewrite mode, set the internal clock frequency 4.0 MHz or less using the main clock division ratio selection bits (bit 6, 7 at 003B16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash memory cannot be used during EW0 mode .
(3) Interrupts inhibited against use
The interrupts cannot be used during EW0 mode because they refer to the internal data of the flash memory. In the EW1 mode, the interrupts cannot be used during program operation or erase operation which is disabled erase suspend function.
(4) Watchdog timer
In case of the watchdog timer has been running already, the internal reset generated by watchdog timer underflow does not happen, because of watchdog timer is always clearing during program or erase operation.
(5) Reset
Reset is always valid. In case of CNVSS = H when reset is released, boot mode is active. So the program starts from the address contained in address FFFC16 and FFFD16 in boot ROM area.
Feb 18, 2005 page 65 of 85 REJ03B0122-0101
7512 Group
Software Commands (CPU Rewrite Mode)
Table 16 lists the software commands. After setting the CPU Rewrite Mode Select Bit of the flash memory control register to "1", execute a software command to specify an erase or program operation. Each software command is explained below. qRead Array Command (FF16) The read array mode is entered by writing the command code "FF16" in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (D0 to D7). The read array mode is retained intact until another command is written. qRead Status Register Command (7016) The read status register mode is entered by writing the command code "7016" in the first bus cycle. The contents of the status register are read out at the data bus (D0 to D7) by a read in the second bus cycle. The status register is explained in the next section. In the EW1 mode, do not execute this command. qClear Status Register Command (5016) This command is used to clear the bits SR4 and SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code "5016" in the first bus cycle. qProgram Command (4016) Program operation starts when the command code "4016" is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification will start. Whether the write operation is completed can be confirmed by _____ reading the status register or the RY/BY Status Flag. ____ The RY/BY Status Flag is "0" (busy) during write operation and "1" (ready) when the write operation is completed as is the status register bit 7. Table 16 List of software commands (CPU rewrite mode)
Do not execute this command for rewrite control program address in the EW1 mode. In the E/W0 mode, when the program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus (D0 to D7). The status register bit 7 (SR7) is set to "0" at the same time the write operation starts and is returned to "1" upon completion of the write operation. In this case, the read status register mode remains active until the read array command (FF16) is written.
Start Write 4016 Write Write address Write data Status register read
RY/BY status flag = "1 "?
NO
YES NO
Program status flag = "0 "?
Program error
YES Program completed
Fig. 73 Program flowchart
Command Read array Read status register Clear status register Program Block erase
Cycle number 1 2 1 2 2
Mode Write Write Write Write Write
First bus cycle Data Address (D0 to D7) X
(Note 1)
Second bus cycle Data Mode Address (D0 to D7)
FF16 7016 5016 4016 2016 Write Write WA (Note 3) BA
(Note 4)
X X X X
Read
X
SRD
(Note 2)
WD (Note 3) D016
Notes 1: X denotes a given address in the User ROM area . 2: SRD = Status Register Data 3: WA = Write Address, WD = Write Data 4: BA = Block Address to be erased (Input the maximum address of each block.)
Feb 18, 2005 page 66 of 85 REJ03B0122-0101
7512 Group
qBlock Erase Command (2016/D016) By writing the command code "2016" in the first bus cycle and the confirmation command code "D016" and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. Whether the block erase operation is completed can be confirmed ____ by reading the status register or the RY/BY Status Flag of flash memory control register. ____ The RY/BY Status Flag is "0" during block erase operation and "1" when the block erase operation is completed as is the status register bit 7. In case of using erase suspend function in the EW0 mode, check that the erase sequence is shifted to erase suspend mode with erase suspend flag. Reading the erase status flag after block erase, the result of the block erase is gotten. Do not execute this command for rewrite control program address in the EW1 mode. In the EW0 mode, at the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. The status register bit 7 (SR7) is set to "0" at the same time the block erase operation starts and is returned to "1" upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written.
Start
Write 2016
Write
D016 Block address
Status register read
RY/BY status flag = "1 "?
NO
YES NO Erase status flag = "0 "? Erase error
YES Erase completed
Fig. 74 Erase flowchart in no erase suspend
Feb 18, 2005 page 67 of 85 REJ03B0122-0101
7512 Group
Status Register (SRD)
The status register shows the operating status of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways: in the EW0 mode. (1) By reading an arbitrary address from the User ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the User ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input. Also, the status register can be cleared by writing the clear status register command (5016). After reset, the status register is set to "8016". Table 17 shows the status register. Each bit in this register is explained below. *Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. This bit is set to "0" (busy) during write or erase operation and is set to "1" when these operations ends. After power-on, the sequencer status is set to "1" (ready). *Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to "1". When the erase status is cleared, it is set to "0". *Program status (SR4) The program status indicates the operating status of write operation. When a write error occurs, it is set to "1". The program status is set to "0" when it is cleared. If "1" is written for any of the SR5 and SR4 bits, the program, erase all blocks, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Also, if any commands are not correct, both SR5 and SR4 are set to "1".
Table 17 Definition of each bit in status register (SRD)
Symbol SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0)
Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved
Definition "1"
Ready Terminated in error Terminated in error -
"0"
Busy Terminated normally Terminated normally -
Feb 18, 2005 page 68 of 85 REJ03B0122-0101
7512 Group
Full Status Check
By performing full status check, it is possible to know the execution results of erase and program operations. Figure 75 shows a
full status check flowchart and the action to be taken when each error occurs.
Read status register
Program status flag = "1 "? Erase status flag = "1 "?
YES
Command sequence error
Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly.
NO NO Should an erase error occur, the block in error cannot be used.
Erase status flag = "0 "?
Erase error
YES NO Should a program error occur, the block in error cannot be used.
Program status flag = "0 "?
Program error
YES
End (erase, program)
Note: When one of erase status flag and program status flag is set to "1", none of the read array, the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands.
Fig. 75 Full status check flowchart and remedial procedure for errors
Feb 18, 2005 page 69 of 85 REJ03B0122-0101
7512 Group
Functions To Inhibit Rewriting Flash Memory Version
To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode. qROM Code Protect Function (in Parallel I/O Mode) The ROM code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the ROM code protect control (address FFDB16) in parallel I/O mode. Figure 76 shows the ROM code protect control (address FFDB16). (This address exists in the User ROM area.) If one or both of the pair of ROM Code Protect Bits is set to "0", the ROM code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. The
ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM Code Protect Reset Bits are set to "00", the ROM code protect is turned off, so that the contents of internal flash memory can be read out or modified. Once the ROM code protect is turned on, the contents of the ROM Code Protect Reset Bits cannot be modified in parallel I/O mode. Use the CPU rewrite mode to rewrite the contents of the ROM Code Protect Reset Bits. Rewriting of only the ROM code protect control address (address FFDB16) cannot be performed. When rewriting the ROM code protect reset bit, rewrite the whole user ROM area (block 0) containing the ROM code protect control address.
b7
b0
1 1 ROM code protect control register (address FFDB16) (Note 1)
ROMCP
Reserved bits ("1" at read/write) ROM code protect level 2 set bits (ROMCP2) (Notes 1, 2)
b3b2
0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled
ROM code protect reset bits (ROMCR) (Note 3)
b5b4
0 0: Protect removed 0 1: Protect set bits effective 1 0: Protect set bits effective 1 1: Protect set bits effective ROM code protect level 1 set bits (ROMCP1) (Note 2)
b7b6
0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled Notes 1: When ROM code protect is turned on, the internal flash memory is protected against readout or modification in parallel I/O mode. 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be modified in parallel I/O mode, they need to be rewritten in CPU rewrite mode.
Fig. 76 Structure of ROM code protect control
Feb 18, 2005 page 70 of 85 REJ03B0122-0101
7512 Group
(2) Parallel I/O Mode
Parallel I/O mode is the mode which parallel output and input software command, address, and data required for the operations (read, program, erase, etc.) to a built-in flash memory. Use the exclusive external equipment flash programmer which supports the 7512 Group (flash memory version). Refer to each programmer maker's handling manual for the details of the usage.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 13 can be rewritten. Both areas of flash memory can be operated on in the same way. The boot ROM area is 4K bytes in size. It is located at addresses F00016 through FFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the Boot ROM area, an erase block operation is applied to only one 4K byte block.
Feb 18, 2005 page 71 of 85 REJ03B0122-0101
7512 Group
Electrical characteristics for Flash ROM E/W Cycles Table 18 Characteristics (Note 1) for 100 E/W cycle products (VCC = 2.5V2%, Ta = 0 to 60 oC, unless otherwise noted) Symbol -- -- -- Parameter Condition Limits Typ. (Note 2) 75 0.2 0.4 0.7 20 Unit cycle s s s s ms year
Min. 100 (Note 4)
Max.
td(SR-ES) --
Erase/Write cycle (Note 3) Byte write time VCC=2.5V, Ta=25C Block erase time 2Kbyte block VCC=2.5V, Ta=25C 8Kbyte block 16Kbyte block Time delay from Suspend Request until Erase Suspend Data retention time (Note 5)
600 9 9 9 8
Table 19 Characteristics (Note 6) for 1000 E/W cycle products [Block A and Block B (Note 7)] (VCC = 2.5V2%, Ta = -20 to 85 oC, unless otherwise noted) Symbol -- -- -- td(SR-ES) Parameter Condition Limits Typ. (Note 2) 100 0.3 8 Unit cycle s s ms
Min.
Max.
Erase/Write cycle (Note 3, 8, 9) 1000 (Note 4) Byte write time VCC=2.5V, Ta=25C Block erase time (2Kbyte block) VCC=2.5V, Ta=25C Time delay from Suspend Request until Erase Suspend
Notes 1: Specified for all blocks. 2: VCC=2.5V; Ta=25C. 3: Definition of E/W cycle: Each block may be written to a variable number of times - up to a maximum of the total number of distinct byte addresses for every block erase. Performing multiple writes to the same address before an erase operation is prohibited. 4: Maximum number of E/W cycles for which operation is guaranteed. 5: At Ta=55C condition 6: Specified for Block A and Block B E/W cycles > 100 7: To reduce the number of E/W cycles, a block erase should ideally be performed after writing as many different byte addresses (only one time each) as possible. It is important to track the total number of block erases. 8: Should erase error occur during block erase, attempt to execute clear status register command, then block erase command at least three times until erase error disappears. 9: Customers desiring E/W failure rate information should contact their Renesas technical support representative.
Erase suspend request bit (Interrupt request) Erase suspend flag td(SR-ES)
Fig. 77 The transition of the timing of the erase / erase suspend
Feb 18, 2005 page 72 of 85 REJ03B0122-0101
7512 Group
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1." After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
Serial interface
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to "1." Serial I/O continues to output the final bit from the TXD pin after transmission is completed. SOUT2 pin for serial I/O2 goes to high impedance after transfer is completed. When in serial I/Os 1 and 3 (clock-synchronous mode) or in serial I/O2, an external clock is used as synchronous clock, write transmission data to the transmit buffer register or serial I/O2 register, during transfer clock is "H."
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction.
A/D Converter
The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) is at least on 500 kHz during an A/D conversion. Do not execute the STP instruction during an A/D conversion.
Decimal Calculations
* To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. * In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid.
Instruction Execution Time
The instruction execution time is obtained by multiplying the period of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The period of the internal clock is double of the XIN period in high-speed mode.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
* The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register.
NOTES ON USAGE Handling of Power Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin), and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F-0.1 F is recommended.
Ports
The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The instruction with the addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers.
Power Source Voltage
When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation.
Feb 18, 2005 page 73 of 85 REJ03B0122-0101
7512 Group
ELECTRICAL CHARACTERISTICS
Table 20 Absolute maximum ratings (Executing flash memory mode, flash memory electrical characteristics is applied.) Symbol VCC VI VI VI VI VO VO Pd Topr Tstg Parameter Conditions Power source voltage Input voltage P00-P07, P20, P21, P26, P27, P30-P35, P40-P42, P45, ADVREF, AVCC, ISENS1 Input voltage P10-P17, P22-P25, P43, P44 All voltages are based on VSS. Input voltage RESET, XIN Output transistors are cut off. Input voltage CNVSS Output voltage P00-P07, P20, P21, P26, P27, P30-P35, P40-P42, P45, XOUT Output voltage P10-P17, P22-P25, P43, P44 Power dissipation Ta = 25 C Operating temperature Storage temperature Ratings -0.3 to 3.2 -0.3 to VCC +0.3 -0.3 to 5.8 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to 5.8 300 -20 to 85 -40 to 125 Unit V V V V V V V mW C C
Table 21 Recommended operating conditions (1) (VCC = 2.5V2%, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC VSS ADVREF ADVSS VIA AVCC AVSS ISENS0 ISENS1 VIH VIH VIH VIH VIH VIL VIL VIL VIL VIL Parameter Power source voltage (At 4 MHz) Power source voltage A/D convert reference voltage A/D convert power source voltage Analog input voltage AN0-AN5, AN8-AN11 Analog power source voltage Analog power source voltage Analog input voltage Analog input voltage "H" input voltage P00-P07, P20, P21, P26, P27, P30-P35, P40-P42, P45 "H" input voltage P10-P17, P22-P25, P43, P44 "H" input voltage (when I2C-BUS input level is selected) SDA1, SDA2, SCL1, SCL2 "H" input voltage (when SMBUS input level is selected) SDA1, SDA2, SCL1, SCL2 ____________ "H" input voltage RESET, XIN, CNVSS "L" input voltage P00-P07, P10-P17, P20-P27, P30-P35, P40-P45 "L" input voltage (when I2C-BUS input level is selected) SDA1, SDA2, SCL1, SCL2 "L" input voltage (when SMBUS input level is selected) SDA1, SDA2, SCL1, SCL2 ____________ "L" input voltage RESET, CNVSS "L" input voltage XIN Min. 2.45 2.0 0 ADVSS 2.45 2.5 0 0 VCC 2.55 Limits Typ. 2.5 0 Max. 2.55 VCC Unit V V V V V V V V V V V V V V V V V V V
-0.2 0.8VCC 0.8VCC 0.7VCC 1.4 0.8VCC 0 0 0 0 0
0.2 VCC 5.8 5.8 5.8 VCC 0.2VCC 0.3VCC 0.6 0.2VCC 0.16VCC
Feb 18, 2005 page 74 of 85 REJ03B0122-0101
7512 Group
Table 22 Recommended operating conditions (2) (VCC = 2.5V2%, Ta = -20 to 85 C, unless otherwise noted) Symbol IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) f(XIN) "H" total peak output current "H" total peak output current "L" total peak output current "L" total peak output current "L" total peak output current "H" total average output current "H" total average output current "L" total average output current "L" total average output current "L" total average output current "H" peak output current Parameter P00-P07, P30-P35 (Note 1) P20, P21, P26-P27, P40-P42, P45 (Note1) P00-P07, P30-P35 (Note 1) P10-P17 (Note1) P20-P27,P40-P45 (Note1) P00-P07, P30-P35 (Note1) P20, P21, P26, P27,P40-P42, P45 (Note1) P00-P07, P30-P35 (Note1) P10-P17 (Note 1) P20-P27,P40-P45 (Note1) P00-P07, P20, P21, P26, P27, P30-P35, P40-P42, P45 (Note 2) "L" peak output current P00-P07, P20-P27, P30-P35, P40-P45 (Note 2) "L" peak output current P10-P17 (Note 2) "H" average output current P00-P07, P20, P21, P26, P27, P30-P35, P40-P42, P45 (Note 3) "L" average output current P00-P07, P20-P27, P30-P35, P40-P45 (Note 3) "L" peak output current P10-P17 (Note 3) Main clock input oscillation frequency (VCC = 2.5V 2%) (Note 4) Sub-clock input oscillation frequency (VCC = 2.5V 2%) (Note 4,5) Min. Limits Typ. Max. -80 -80 80 80 80 -40 -40 40 40 40 -10 10 20 -5 5 15 5 50 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA MHZ KHZ
4 32.768
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms. 4: When the oscillation frequency has a duty cycle of 50%. 5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
Feb 18, 2005 page 75 of 85 REJ03B0122-0101
7512 Group
Table 23 Electrical characteristics (1) (VCC = 2.5V2%, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol VOH Parameter "H" output voltage P00-P07, P20, P21, P26, P27, P30-P35, P40-P42, P45 (Note) "L" output voltage P00-P07, P20-P27, P30-P35, P40-P45 "L" output voltage P10-P17 Hysteresis CNTR0, CNTR1, INT0-INT3 Hysteresis RxD, SCLK1, SIN2, SCLK2 ____________ Hysteresis RESET "H" input current P00-P07, P20, P21, P26, P27, P30-P35, P40-P42, P45 "H" input current ISENS0, ISENS1 ____________ "H" input current RESET, CNVSS "H" input current XIN "L" input current P00-P07, P10-P17, P20-P27 P30-P35, P40-P45 "L" input current ISENS0, ISENS1 ____________ "L" input current RESET,CNVSS "L" input current XIN RAM hold voltage Test conditions IOH =-1.0 mA VCC =2.5V2% Min. VCC -0.8 Typ. Max. Unit V
VOL
IOL =1.0 mA VCC =2.5V2% IOL =10 mA VCC =2.5V2% 0.4 0.4 0.4 VI = VCC
0.8
V
VOL VT+-VT- VT+-VT- VT+-VT- IIH
0.8
V V V V A
5.0
IIH IIH IIH IIL
VI = VCC VI = VCC VI = VCC VI = VSS
1.0 5.0 4 -5.0
A A A A
IIL IIL IIL VRAM
VI = VSS VI = VSS VI = VSS When clock stopped
-1.0 -5.0 -4 2.0 2.55
A A A V
Feb 18, 2005 page 76 of 85 REJ03B0122-0101
7512 Group
Table 24 Electrical characteristics (2) (VCC = 2.5V2%, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol ICC Parameter Power source current Test conditions High-speed mode f(XIN) = 4 MHz or high-speed RC oscillating (4MHZ) f(XCIN) = 32.768 kHz or RC oscillating Output transistors "off" Current integrator and current detector stopped High-speed mode f(XIN) = 4 MHz or high-speed RC oscillating (4MHZ) (in WIT state) f(XCIN) = 32.768 kHz Output transistors "off" Current integrator and current detector stopped Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz or 32kHz RC oscillating Output transistors "off" Current integrator and current detector stopped Low-speed mode f(XIN) = stopped cristal f(XCIN) = 32.768 kHz (cristal) or 32kHz RC oscillating (in WIT state) Output transistors "off" RC Current integrator and current detector stopped Middle-speed mode f(XIN) = 4 MHz or high-speed RC oscillating (4MHZ) f(XCIN) = stopped Output transistors "off" Current integrator and current detector stopped Middle-speed mode f(XIN) = 4 MHz or high-speed RC oscillating (4MHZ) (in WIT state) f(XCIN) = stopped Output transistors "off" Current integrator and current detector stopped Increment when A/D conversion is executed f(XIN) = 4 MHz or high-speed RC oscillating (4MHZ) Flash memory write f(XIN) = 4MHZ VCC = 2.5V Flash memory erase f(XIN) = 4MHZ VCC = 2.5V Min. Typ. Max. Unit
1.5
2.5
mA
0.8
mA
420
A
6.4
A
30
A
1.0
mA
0.8
mA
200 12 22
A mA mA
Feb 18, 2005 page 77 of 85 REJ03B0122-0101
7512 Group
Table 25 Electrical characteristics (3) (VCC = 2.5V2%, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol ICC Limits Parameter Power source current Test conditions Increment when current integrator is executed Increment when Short current detector over current detector Over current detector is executed. Charge over current detector Wake up current detector Two detectors used other than Wake up current detector Three detectors used other than Wake up current detector Wake up current detector and another use Wake up current detector and other two used Wake up current detector and other three used All oscillation stopped Ta = 25 C (Note) (in STP state) Output Ta = 85 C transistors "off" Min. Typ. 800 20 20 20 25 30 40 35 45 55 Max. Unit A A A A A A A A A A 1.0 10 A A
0.1
Note : When using the 32kHz RC oscillation circuit or the XCIN-XCOUT oscillation, before STP instruction execution select the modes other than the low-speed mode with the main clock division ratio selection bit (CM7, CM6) and then set ports P21 and P20 to output port ("L" output).
Feb 18, 2005 page 78 of 85 REJ03B0122-0101
7512 Group
Table 26 High-speed RC oscillation circuit electrical characteristics (VCC = AVCC = 2.5V2%, VSS =AVSS = 0V, Ta = -20 to 85 C, unless otherwise noted) Symbol f4MRC f4MRCS Parameter Oscillating frequency ajustment width (Note) Oscillating frequency shift by temperature Test conditions f(XIN)=4 to 5 MHZ 0.2 Limits Min. Typ. Max. Unit % %/C
3.0
0.5
Notes : The bigger setting value of the high-speed RC oscillator frequency set up register (address 0FF216) makes the oscillating frequency of the highspeed RC oscillation circuit lower. However, since the oscillating frequency is set higher when setting the values from 7F16 to 8016 or from BF16 to C016, be careful of frequency adjustment by software.
Table 27 32kHz RC oscillation circuit electrical characteristics (VCC = AVCC = 2.5V2%, VSS =AVSS = 0V, Ta = -20 to 85 C, unless otherwise noted) Symbol - Parameter Test conditions Limits Min. Typ. Max. 10 0.07 0.5 0.5 2 Unit
External registor, and capacitor tolerance Total tolerance of the resistor and capacitor when External registor=91k when External capacitor=100pF Oscillating frequency adjustment resolution Oscillating frequency shift by VCC voltage Ta=25 C Oscillating frequency shift by temperature VCC=AVCC=2.5V, -20 to 85 C Oscillating frequency shift by VCC voltage and temperature
% kHz % % %
- - - -
Oscillation frequency
8016
C016
High-speed RC oscillator frequency set up register
Fig. 78 High-speed RC oscillation circuit register value - Oscillating frequency characteristics
Feb 18, 2005 page 79 of 85 REJ03B0122-0101
7512 Group
Table 28 A/D converter characteristics (VCC = 2.5 2%, VSS = AVSS = 0 V, Ta = -20 to 85 C, f(XIN) = 4MHz, f(XCIN) = 32.768KHz, unless otherwise noted) Symbol - - tCONV Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Test conditions Min. Limits Typ. Max. 10 4 61 40 35 100 0.5 Unit bit LSB tc() s k A A A
High-speed mode, middle-speed mode Low-speed mode 40
RLADDER IVREF II(AD)
Ladder resistor Reference power source input current A/D port input current
VREF "on" VREF = 2.5 V VREF "off"
140 5.0 5.0
Table 29 Easy thermal sensor electrical characteristics (VCC = 2.5V2%, VSS =AVSS = 0V, Ta = -20 to 85 C, f(XIN) = 4MHz, f(XCIN) = 32.768KHz) Symbol - - Parameter Easy thermal sensor output voltage at room temperature The rate of the easy thermal sensor output voltage by temperature Test conditions Min. Ta=27C VCC = VREF = 2.5 V Limits Unit Typ. 1.38 3.4 Max. V mV/ C
Table 30 Current integrator electrical characteristics (VCC = AVCC = 2.5V2%, VSS =AVSS = 0V, Ta = -20 to 85 C, f(XIN) = 4MHz, f(XCIN) = 32.768KHz) Symbol t INF V ISENS1 AD AC t RD t RC b' V REFD V REFC - Parameter Test conditions Limits Min. -0.15 0.68 0.68 Typ. 125 1.00 1.00 300 300 0.1 -0.1 0.2 1.35 1.35 Max. Unit ms V V*sec V*sec ns ns - V V % %
Integrate period ISENS1 input range Integrate coefficient of integrator for discharge Integrate coefficient of integrator for charge Reset time of integrator for discharge Reset time of integrator for charge Count value at 0V input Internal reference voltage for discharge integrator Internal reference voltage for charge integrator linearity error after reset time caribration VCC=2.5V2%, Ta=0 to 60 C VCC=2.5V2%, Ta=-20 to 85 C
-2400 0.09 -0.11
2400 0.11 -0.09 1 3
tINF
tINF tCAL
tINF
1.75V
Integrator output
1.25V 0.75V
tRD, tRC Discharge signal for the integrator
tRD, tRC
tRD, tRC
tRD, tRC
tRD, tRC
Note : All signals are internals.
Fig. 79 Current integrator timing diagram
Feb 18, 2005 page 80 of 85 REJ03B0122-0101
7512 Group
Count value Discharge
* VISENS1 nD - b = TINF AD
nREFD
n'D - b '=
TINF * VISENS1 AD + tRD * VISENS1
b' VREFC c VREFD VISENS1 ISENS1 input voltage
b=
TINF * b' TINF-tRD * b'
n'C = ACTINF * (VISENS1-c) + tRC * (VISENS1-c) nC =
TINF * (VISENS1-c) AC
c=
vREFD * b nREFD-b
Charge
Fig. 80 VISENS1-Count value characteristics of current integrator
Table 31 Over current detector electrical characteristics (VCC = AVCC = 2.5V2%, VSS =AVSS = 0V, Ta = -20 to 85 C, f(XIN) = 4MHz, f(XCIN) = 32.768MHz) Symbol - - - - - - - - Parameter Discharge short current detect voltage error Discharge over current detect voltage error Charge over current detect voltage error Wake up detect voltage Discharge short current detect time error Discharge over current detect time error Discharge over current detect time error Wake up detect time 58.6 T.B.D. T.B.D. 62.5 s ms 8 10 Conditions Limits Min. Typ. Max. 15 15 15 12 30.5 Unit mV mV mV mV s
Feb 18, 2005 page 81 of 85 REJ03B0122-0101
7512 Group
TIMING REQUIREMENTS
Table 32 Timing requirements (VCC = 2.5V2%, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD-SCLK1) th(SCLK1-RxD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT3 input "H" pulse width INT0 to INT3 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 clock input set up time Serial I/O1 clock input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 clock input set up time Serial I/O2 clock input hold time Limits Min. 20 250 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Unit XIN cycles ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is "0" (UART).
Table 33 Switching characteristics (VCC = 2.5V2%, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH (SCLK1) tWL (SCLK1) td (SCLK1-TXD) tv (SCLK1-TXD) tr (SCLK1) tf (SCLK1) tWH (SCLK2) tWL (SCLK2) td (SCLK2-SOUT2) tv (SCLK2-SOUT2) tf (SCLK2) tr (CMOS) tf (CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Test conditions Limits Min. Typ. tC(SCLK1)/2-50 tC(SCLK1)/2-50 -30 50 50 tC(SCLK2)/2-240 tC(SCLK2)/2-240 400 0 20 20 50 50 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
350
Fig. 82
Notes 1: For tWH(SCLK1), tWL(SCLK1), when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register (bit 7 of address 001516) is "0". 3: The XOUT pin is excluded.
Feb 18, 2005 page 82 of 85 REJ03B0122-0101
7512 Group
MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS
Table 34 Multi-master I2C-BUS bus line characteristics Standard clock mode High-speed clock mode Symbol tBUF tHD;STA tLOW tR Bus free time Hold time for START condition Hold time for SCL clock = "0" Rising time of both SCL and SDA signals Parameter Min. 4.7 4.0 4.7 1000 Max. Min. 1.3 0.6 1.3 20+0.1Cb (Note) tHD;DAT tHIGH tF Data hold time Hold time for SCL clock = "1" Falling time of both SCL and SDA signals 0 4.0 300 0 0.6 20+0.1Cb (Note) tSU;DAT tSU;STA tSU;STO Data setup time Setup time for repeated START condition Setup time for STOP condition 250 4.7 4.0 100 0.6 0.6 ns s s 300 0.9 s s ns 300 Max. Unit s s s ns
Note: Cb = total capacitance of 1 bus line
SDA
tBUF tLOW tR tF
Sr P
tHD:STA
tsu:STO
SCL
P
S
tHD:STA
tHD:DAT
tHIGH
tsu:DAT
tsu:STA
S : START condition Sr: RESTART condition P : STOP condition
Fig. 81 Timing diagram of multi-master I2C-BUS
1k
Measurement output pin 100pF
Measurement output pin 100pF
CMOS output
N-channel open-drain output
Fig. 82 Circuit for measuring output switching characteristics (1)
Fig. 83 Circuit for measuring output switching characteristics (2)
Feb 18, 2005 page 83 of 85 REJ03B0122-0101
7512 Group
tC(CNTR)
CNTR0 CNTR1
tWH(CNTR) 0.8VCC 0.2VCC
tWL(CNTR)
tWH(INT)
tWL(INT) 0.2VCC
INT0 to INT3
0.8VCC
tW(RESET)
RESET
0.2VCC
0.8VCC
tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC
XIN
0.8VCC
SCLK1 SCLK2
tf
tC(SCLK1), tC(SCLK2) tWL(SCLK1), tWL(SCLK2) tWH(SCLK1), tWH(SCLK2) tr 0.2VCC tsu(RxD-SCLK1), tsu(SIN2-SCLK2) 0.8VCC th(SCLK1-RxD), th(SCLK2-SIN2)
RXD SIN2
td(SCLK1-TXD), td(SCLK2-SOUT2)
0.8VCC 0.2VCC tv(SCLK1-TXD), tv(SCLK2-SOUT2)
TXD SOUT2
Fig. 84 Timing diagram
Feb 18, 2005 page 84 of 85 REJ03B0122-0101
7512 Group
PACKAGE OUTLINE
48P6Q-A
EIAJ Package Code LQFP48-P-77-0.50
Recommended
JEDEC Code - Weight(g) - Lead Material Cu Alloy
Plastic 48pin 77mm body LQFP
MD
e
HD D
48 37
1
36
b2
I2 Recommended Mount Pad
Symbol HE A A1 A2 b c D E e HD HE L L1 Lp
A3
12
25
13
24
A F e A2 L1
y
b
L Detail F
Lp
x y b2 I2 MD ME
x
M
Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 1.4 - - 0.17 0.22 0.27 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 0.5 - - 8.8 9.0 9.2 8.8 9.0 9.2 0.35 0.5 0.65 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.08 0.1 - - 0 8 - 0.225 - - 1.0 - - 7.4 - - - - 7.4
E
A1
Feb 18, 2005 page 85 of 85 REJ03B0122-0101
c
A3
ME
REVISION HISTORY
Rev. Date Page 1.00 Nov.10, 2004 1.01 Feb.18, 2005 - 14 First edition issued
7512 Group Data Sheet
Description Summary
Fig.11 Ports P44 and P45 are partly revised.
(1/1)
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
(c) 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon 2.0

▲Up To Search▲

Price & Availability of 7512

	To Download 7512 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .